Digi NS9215, Hardware Reference Manual, Page: 454 / 517

I 2 C M A S T E R / S L A V E I N T E R F A C E
Configuration register
454
Hardware Reference NS9215
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C o n f i g u r a t i o n r e g i s t e r
Address: 9005 000C
The Configuration register controls the timing on the I
2
C bus. This register also
controls the external interrupt indication, which can be disabled.
The I
2
C bus clock timing is programmable by the
scl_ref
value (
D08:00
). The timing
parameter for standard mode is as follows:
I
2
C_bus_clock = clk / ((CLREF*2) + 4 + scl_delay)
clk = PLL Clk Out/4
Notes:
To determine the “PLL Clk Out” frequency, see the “PLL configuration and control system
block diagram” on page 152 and the “PLL Configuration register” on page 186. In noisy environments
and fast-mode transmission, spike filtering can be applied to the received I
2
C data and clock signal. The
spike filter evaluates the incoming signal and suppresses spikes. The maximum length of the suppressed
spikes can be specified in the spike filter width field of the Configuration register.
Timing parameter
for fast-mode
This is the timing parameter for fast-mode:
I
2
C_bus_clock = (4 / 3) x (clk / ((CLREF*2) + 4 + scl_delay))
scl_delay
is influenced by the SCL rise time.
Register
Register bit
assignment
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
Reserved
CLREF IRQD TMDE VSCD SFW
s
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15 R/W IRQD 0
Mask the interrupt to the ARM CPU
(
irq_dis
)
Must be set to 0.
D14 R/W TMDE 1 Timing characteristics of serial data and serial
clock
0Standard mode
1Fast mode
D13 R/W VSCD 1 Virtual system clock divider for master and
slave
Must be set to 0.