MB86R02 ‘Jade-D’ Hardware Manual V1.64
22-28
only)
Bit 18 -
17
ChanSel12
Channel selection for Pad i=12 for RSDS: 00b=clk, 01b=channel(i-1), 10b=reserved, 11b=const0, for TTL: 00b=clk, 01b=channel i*2-
1, 10b=INV (from inversion control function), 11b=const 0
Bit 14
NDelay12
N-pin Padcell 12 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13
Delay12
Pad 12 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7
InOut12
output enable control, 0b=input enabled, 1b=output enabled
Bit 6
NPolarity12
N-pin of Padcell 12 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5
Polarity12
Pad 12 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4
Mode12
Pad 12 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0 Boost12
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
Содержание MB86R02
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Страница 76: ...3 2 MB86R02 Jade D Hardware Manual V1 64 Figure 3 1 Memory map 1 ...
Страница 77: ...3 3 MB86R02 Jade D Hardware Manual V1 64 Figure 3 2 Memory map 2 ...
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Страница 214: ...11 7 MB86R02 Jade D Hardware Manual V1 64 15 16 cycles initial value ...
Страница 216: ...11 9 MB86R02 Jade D Hardware Manual V1 64 0000011 b 4MB 0111111 b 64MB 0000111 b 8MB 1111111 b 128MB ...
Страница 304: ...16 5 MB86R02 Jade D Hardware Manual V1 64 The flow of a read action is shown below Figure 16 5 Read process flow ...
Страница 497: ...18 139 MB86R02 Jade D Hardware Manual V1 64 VSYNC is output 1 dot clock faster than HSYNC ...
Страница 558: ...18 200 MB86R02 Jade D Hardware Manual V1 64 017 S S S S S S S S Int Frac 060 018 dBdy S S S S S S S S Int Frac ...
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Страница 682: ...22 2 MB86R02 Jade D Hardware Manual V1 00 FUJITSU PROPRIETARY AND CONFIDENTIAL ...
Страница 684: ...22 2 MB86R02 Jade D Hardware Manual V1 00 FUJITSU PROPRIETARY AND CONFIDENTIAL Figure 22 14 TCON flow diagram ...
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