11-13
MB86R02 ‘Jade-D’ Hardware Manual V1.64
11.8 Example of access waveform
Word read access to 16 bit width SRAM/NOR Flash
01
X
D01
MEM_EA[24:1]
00
D00
X
MEM_ED[15:0]
MEM_XRD
MEM_XWR[1:0]
MEM_XCS[4/2/0]
Internal clock
MEM_RDY
tRACC + tRACC cycle
tRADC = Read address setup cycle
tRADC
tRACC = Read access cycle
tRADC
tRIDLC
tRIDLC = Read idle cycle
Word write access to 16 bit width SRAM/NOR Flash
01
X
D01
MEM_EA[24:1]
00
D00
X
MEM_ED[15:0]
MEM_XRD
MEM_XWR[1:0]
MEM_XCS[4/2/0]
Internal clock
MEM_RDY
tWACC
tWADC = Write address setup cycle
tWADC
tWACC = Write access cycle
tWADC
tWIDLC
tWWEC = Write enable cycle
tWWEC
X
tWWEC
tWIDLC = Write idle cycle
1 cycle
1 cycle
tWACC
Содержание MB86R02
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Страница 304: ...16 5 MB86R02 Jade D Hardware Manual V1 64 The flow of a read action is shown below Figure 16 5 Read process flow ...
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