Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
List of Figure
Figure 2-1 External interrupt/event controller block diagram ........................................................................... 41
Figure 2-2 External interrupt GPIO mapping .................................................................................................... 43
Figure 3-1 Bus architecture ............................................................................................................................... 48
Figure 3-2 Bus address map .............................................................................................................................. 50
Figure 4-1 Power supply block diagram ............................................................................................................ 78
Figure 4-2 Waveforms of power-on reset and power-down reset ...................................................................... 79
Figure 4-3 PVD threshold waveform................................................................................................................. 80
Figure 6-1 System reset generation ................................................................................................................. 101
Figure 6-2 Clock Tree ...................................................................................................................................... 103
Figure 6-3 HSE/LSE clock source ................................................................................................................... 104
Figure 7-1 Basic structure of I/O port .............................................................................................................. 136
Figure 7-2 Input float/pull-up/pull-down configuration .................................................................................. 138
Figure 7-3 Output mode configuration ............................................................................................................ 139
Figure 7-4 Alternate function configuration .................................................................................................... 140
Figure 7-5 High impedance analog mode configuration ................................................................................. 141
Figure 8-1 DMA block diagram....................................................................................................................... 184
Figure 8-2 DMA1 request mapping ................................................................................................................. 190
Figure 8-3 DMA2 request mapping ................................................................................................................. 192
Figure 9-1 Block diagram of a single ADC ..................................................................................................... 205
Figure 9-2 ADC clock ...................................................................................................................................... 207
Figure 9-3 ADC1 and ADC2 channel pin connections .................................................................................... 208
Figure 9-4 ADC3 and ADC4 channel pin connections .................................................................................... 210
Figure 9-5 Timing diagram .............................................................................................................................. 212
Figure 9-6 Injection conversion delay ............................................................................................................. 214
Figure 9-7 Calibration sequence diagram ........................................................................................................ 215
Figure 9-8 Dual ADC Block Diagram ............................................................................................................. 219
Figure 9-9 Schematic diagram of synchronous regular mode conversion of 16 channels ............................... 220
Figure 9-10 Schematic diagram of synchronous injection mode conversion of 4 channels ............................ 221
Figure 9-11 Schematic diagram of fast alternate mode conversion for continuous conversion of 1 channel .. 222
Figure 9-12 Schematic diagram of slow alternate mode conversion for 1 channel ........................................ 223