Nations N32G45 Series, User Manual

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Nations Technologies Inc.
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
6. If current frame transfer ends, DMA operation skips to step 7. If current frame transmission does not end (end
of frame EOF is not received), two things can happen:
a) If RDES0.OWN of next descriptor is 0 and receive frame clearing function is not enabled, RxDMA
controller sets RDES0.DE (descriptor error bit). RxDMA controller clears RDES0.OWN of the current
descriptor to close the descriptor, if frame clearing function is not enabled, sets RDES0.LS, otherwise does
not set RDES0.LS, and then skips to step 8.
b) If RDES0.OWN of next descriptor is 1, RxDMA clears RDES0.OWN to close current descriptor, and then
returns to step 4.
7. If IEEE 1588 timestamp function is enabled, and received frame meets the conditions of the frame that needs to
record the timestamp, DMA controller will write the low and high bits of the acquired timestamp into RDES2
and RDES3 of current descriptor after receiving the frame. At the same time, DMA writes the received status
information returned from MAC into RDES0, clears RDES0.OWN to 0, and sets RDES0.LS to 1;
8. If RDES0.OWN of newly acquired descriptor is 1, RxDMA controller operates jumping step 4; if RDES0.OWN
is 0, received frame will be cleared first (provided that the receive frame clearing function is enabled), and then
RxDMA controller enters suspend state and sets ETH_DMASTS.RU (receive buffer unavailable) to 1;
9. When any write operation is performed to ETH_DMARXPD register or RxFIFO receives the next frame of data,
the suspend state can be exited. When DMA exits suspended state, DMA operation jumps to step 2 and attempts
to re-acquire next descriptor.
MAC initialization using DMA
The MAC initialization process using DMA controller is as follows:
1. Set ETH_DMABUSMOD register bus access related parameters.
2. Set ETH_DMAINTEN register to mask unnecessary interrupt sources.
3. First write the base address of the transmit descriptor list into ETH_DMATXDLADDR register, and then write
the base address of the receive descriptor list into ETH_DMARXDLADDR register.
4. Configure the relevant filter registers as required.
5. Set the values of ETH_MACCFG.FES and ETH_MACCFG.DM according to the register result read from the
external PHY, and select half-duplex or full-duplex communication mode and the communication speed of
10Mbps or 100Mbps. Set ETH_MACCFG.TE and ETH_MACCFG.RE to 1 to enable the transmit engine and
receive engine of MAC.
6. Set ETH_DMAOPMOD.ST and ETH_DMAOPMOD.SR to 1 to enable TxDMA and RxDMA.
Note: If the HCLK frequency configuration is too low, RxFIFO may overflow at startup. It is recommended to enable
RxDMA first, and then set ETH_MACCFG.RE to 1.
Arbiter for TxDMA and RxDMA
DMA arbiter can improve the efficiency of DMA controller through fixed and polling priority arbitration methods.
When ETH_DMABUSMOD.DA is set to 0, the polling priority arbitration method is adopted. If TxDMA and
RxDMA request to access the data bus at the same time, the access priority between TxDMA and RxDMA can be
configured by setting these bits of ETH_DMABUSMOD.PR[1:0] level ratio. When ETH_DMABUSMOD.DA is set