490
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
18.7.11
SDIO data counter register (SDIO_DATCOUNT)
Address offset: 0x30
Reset value: 0x0000 0000
When the DPSM enters the Wait_R or Wait_S state from the idle state, the SDIO_DATCOUNT register loads the
value from the data length register (see SDIO_DATLEN). During the data transfer, the value of this counter is
decremented until it is reduced to 0, then the SDIO_STS.DPSM enters the idle state and sets the data state End mark
DATEND.
Bit Field
Name
Description
31:25
Reserved
Reserved, the reset value must be maintained.
24:0
DATCOUNT
Data count value.
When reading this register, it returns the number of data bytes to be transmitted. Writing this
register has no effect.
Note: This register can only be read at the end of a data transfer.
18.7.12
SDIO status register (SDIO_STS)
Address offset: 0x34
Reset value: 0x0000 0000
SDIO_STS is a read-only register that contains two types of flags:
Static flags (bits[23:22, 10:0]): These bits can be cleared by writing to the SDIO Interrupt Clear Register (see
SDIO_ INTCLR).
Dynamic flags (bits[21:11]): The state of these bits changes according to the part of the logic they correspond
to (eg: FIFO full and empty flags go high or low with data writes to the FIFO).
Bit Field
Name
Description
31:24
Reserved
Reserved, the reset value must be maintained.
23
CEATAF
CE-ATA command completion signal received for CMD61.
