484
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit Field
Name
Description
0: SDIO_CLK is generated on the rising edge of the master clock SDIOCLK.
1: SDIO_CLK is generated on the falling edge of the master clock SDIOCLK.
12:11
BUSMODE
Wide bus mode enable bit.
00: Default bus mode, use SDIO_DAT0.
01: 4-bit bus mode, use SDIO_DAT[3:0].
10: 8-bit bus mode, use SDIO_DAT[7:0].
10
CLKBYP
Clock divider bypass enable bit.
0: Bypass off: SDIOCLK is divided according to the DIV value before driving the SDIO_CLK
output signal.
1: Bypass enabled: SDIOCLK directly drives the SDIO_CLK output signal.
9
PWRCFG
Power saving configuration bit.
To save power, the SDIO_CLK clock output can be turned off by setting the PWRCFG bit when
the bus is idle.
0: SDIO_CLK is always output.
1: SDIO_CLK is only output when there is bus activity.
8
CLOCKEN
Clock enable bit.
0: SDIO_CLK is off.
1: SDIO_CLK is enabled.
7:1
DIV
Clock divide factor.
This field defines the division factor between the input clock (SDIOCLK) and the output clock
(SDIO_CLK):
SDIO_CLK frequency = SDIOCLK/[DIV + 2].
Notice:
1.
When SD/SDIO card or multimedia card is in identification mode, the frequency of SDIO_CLK must be lower
than 400kHz.
2.
When all cards are assigned corresponding addresses, the clock frequency can be changed to the maximum
frequency allowed by the card bus.
3.
This register cannot be written within 7 HCLK clock cycles after writing data. For SD I/O cards, SDIO_CLK
can be stopped during the read wait period, when SDIO_CLKCTRL register does not control SDIO_CLK.
18.7.4
SDIO command argument register (SDIO_CMDARG)
Address offset: 0x08
Reset value: 0x0000 0000
SDIO_CMDARG register contains the 32-bit command parameter, which will be sent to the card as part of the
command.
