Nations N32G45 Series, User Manual

Page: 393 / 838

393 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field Name Description
7
ARPEN ARPEN: Auto-reload preload enable
0: Shadow register disable for TIMx_AR register
1: Shadow register enable for TIMx_AR register
6:4
Reserved Reserved, the reset value must be maintained
3
ONEPM One-pulse mode
0: Disable one-pulse mode, the counter counts are not affected when an update event occurs.
1: Enable one-pulse mode, the counter stops counting when the next update event occurs
(clearing TIMx_CTRL1.CNTEN bit)
2
UPRS Update request source
This bit is used to select the UEV event sources by software.
0: If update interrupt or DMA request is enabled, any of the following events will generate an
update interrupt or DMA request:
–
Counter overflow
–
The TIMx_EVTGEN.UDGN bit is set
1: If update interrupt or DMA request is enabled, only counter overflow will generate update
interrupt or DMA request
1
UPDIS Update disable
This bit is used to enable/disable the Update event (UEV) events generation by software.
0: Enable UEV. UEV will be generated if one of following condition been fulfilled:
–
Counter overflow
–
The TIMx_EVTGEN.UDGN bit is set
Shadow registers will update with preload value.
1: UEV disabled. No update event is generated, and the shadow registers (AR, PSC) keep their
values. If the TIMx_EVTGEN.UDGN bit is set, the counter and prescaler are reinitialized.
0
CNTEN Counter Enable
0: Disable counter
1: Enable counter
13.4.3 Control Register 2 (TIMx_CTRL2)
Offset address
：
0x04