Nations N32G45 Series, User Manual

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330 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field Name Description
00010: 3 times transfers
…
10001: 18 times transfers
7:5 Reserved Reserved, the reset value must be maintained.
4:0 DBADDR[4:0] DMA Base Address
This bit field defines the first address where the DMA accesses the TIMx_DADDR register.
When access is done through the TIMx_DADDR first time, this bit-field specifies the address you
just access. And then the second access to the TIMx_DADDR, you will access the address of
“
DMA Base A 4”
00000: TIMx_CTRL1,
00001: TIMx_CTRL2,
00010: TIMx_SMCTRL,
…
10001: TIMx_BKDT
10010
：
TIMx_DCTRL
11.4.21 DMA transfer buffer register (TIMx_DADDR)
Offset address: 0x4C
Reset value: 0x0000
Bit field Name Description
15:0 BURST[15:0] DMA access buffer.
When a read or write operation is assigned to this register, the register located at the address range
(DMA base a DMA burst length × 4) will be accessed.
DMA base address = The address of TIM TIMx_DCTRL. DBADDR * 4
；
DMA burst len = TIMx_DCTRL.DBLEN + 1.
Example:
If TIMx_DCTRL.DBLEN = 0x3(4 transfers), TIMx_DCTRL.DBADDR = 0xD (TIMx_CCDAT1),
DMA data length = half word, DMA memory address = buffer address in SRAM, DMA peripheral
address = TIMx_DADDR address.
When an event occurs, TIMx will send requests to the DMA, and transfer data 4 times.
For the first time, DMA access to the TIMx_ DADDR register will be mapped to access
TIMx_CCDAT1 register;