Nations N32G45 Series, User Manual

Page: 219 / 838

219 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
enabled at the same time, so as to avoid the wrong trigger conversion of the slave ADC.
2. When working in dual ADC mode, even if DMA is not used to transfer data, DMA needs to be enabled, and the
converted data from the ADC can be read through the data register of the main ADC.
Figure 9-8 Dual ADC Block Diagram
9.9.1 Independent mode
In this mode, each ADC works independently.
9.9.2 Synchronous regular mode
In this mode, a regular sequence is converted, and the external trigger comes from the multiplexer of ADC1, which
is determined by ADC_CTRL2.EXTRSEL[2:0], and ADC2 will be triggered synchronously.
If ADC1 or ADC2 sets ADC_CTRL1.ENDCIEN, when the conversion of the regular sequence of ADC1 or ADC2 is
completed, an ENDC interrupt will be generated, and the converted data will be stored in the ADC_DAT register.
The high half word of ADC_DAT is the conversion data of ADC2. The low half word of ADC_DAT is the conversion
data of ADC1, and 32-bit DMA can be used to transfer the data of ADC_DAT to SRAM.
Note:
1. Do not convert the same channel on 2 ADCs (the sampling times of two ADCs on the same channel cannot overlap).
ADCx_IN1
ADCx_IN2
ADCx_IN15
Gpio
Ports
Data bus
Data register
A
n
a
lo
g
c
h
a
n
n
e
l
m
u
lt
ip
le
x
in
g
Injected
channels
Regular
channels
Analog to
digital
channels
Injected data registers
(4 x 16 bits)
Regular data register
(16 bits)
A
D
C
_
C
T
R
L
2
.
E
X
T
J
T
R
IG
b
it
T
IM
1
_
T
R
G
O
T
IM
1
_
CH
4
T
IM
2
_
T
R
G
O
T
IM
2
_
CH
1
T
IM
4
_
T
R
G
O
T
IM
3
_
CH
4
T
IM8
_CH
4
E
X
T
I_
15
AFIO_RMP_CFG.
ADCx_ETRI bit
A
D
C
_
C
T
R
L
2
.
E
X
T
R
T
R
IG
b
it
T
IM8
_T
RGO
AFIO_RMP_CFG.
ADCx_ETRR bit
ADC_CTRL2.
EXTJSEL[2:0] bits
ADC_CTRL2.
EXTRSEL[2:0] bits
T
IM
1
_
CH
1
T
IM
1
_
CH
2
T
IM
1
_
CH
3
T
IM
2
_
CH
2
T
IM
4
_
CH
4
T
IM
3
_
T
R
G
O
E
X
T
I_
11
Trigger signal for ADC1
Injected
channels
Regular
channels
Analog to
digital
channels
Injected data registers
(4 x 16 bits)
Regular data register
(16 bits)
Dual ADC
contral
ADCx_IN1
ADCx_IN2
ADCx_IN15
Gpio
Ports
A
n
a
lo
g
c
h
a
n
n
e
l
m
u
lt
ip
le
x
in
g
V
TS
V
𝑅𝐸𝐹𝐼𝑁𝑇
V
𝐵𝐴𝑇/2
V
TS
V
𝑅𝐸𝐹𝐼𝑁𝑇
V
𝐵𝐴𝑇/2
ADC1(master)
ADC2(slave)