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Nations Technologies Inc.
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
11.3.15
Debug mode
When the microcontroller is in debug mode (the Cortex-M4 core halted), depending on the DBG_CTRL.TIMx_STOP
configuration in the DBG module, the TIMx counter can either continue to work normally or stop. For more details,
see 29.4.3.
11.3.16
TIMx and external trigger synchronization
TIMx timers can be synchronized by a trigger in slave modes (reset, trigger and gated).
Slave mode: Reset mode
In reset mode, the trigger event can reset the counter and the prescaler updates the preload registers TIMx_AR,
TIMx_CCDATx, and generates the update event UEV (TIMx_CTRL1.UPRS=0).
The following is an example of a reset mode:
1. Channel 1 is configured as input to detect the rising edge of TI1 (TIMx_CCMOD1.CC1SEL=01,
TIMx_CCEN.CC1P=0);
2. The slave mode is selected as reset mode (TIMx_SMCTRL.SMSEL=100), and the trigger input is selected as TI1
(TIMx_SMCTRL.TSEL=101);
3. Start counter (TIMx_CTRL1.CNTEN = 1)
After starting the timer, when TI1 detects a rising edge, the counter resets and restarts counting, and the trigger flag
is set (TIMx_STS.TITF=1);
The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit
on TI1 input.
Figure 11-27 Control circuit in reset mode
TI1
Counter register
60 61 62 63 64 65 66 00 01 02 03
01 02 03
00
UDGN
TITF
Counter clock = ck_cnt = ck_psc
