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to 1, a fixed priority is selected. If TxDMA and RxDMA request to access the data bus at the same time, in this
arbitration mode, RxDMA has a higher access priority to the bus.
Error response to DMA
If DMA has a wrong bus response during the transfer, DMA controller will treat it as a fatal error, stop all operations
immediately, and update the status register ETH_DMASTS. Once this happens, Ethernet peripheral must be reset
and DMA reinitialized before DMA can resume normal operation.
25.4.9
Precision time protocol (PTP)
MAC's Precision Time Protocol (PTP) module mainly supports recording the exact time when PTP packets are sent
and received from the Ethernet port, and returns it to the application. Much of the protocol is implemented by
application software on top of the UDP layer.
For details on Precision Time Protocol (PTP), please refer to the IEEE 1588™ related documentation.
Reference clock source
In IEEE 1588 protocol standard, the upper 32 bits of the 64-bit system reference time are second-level time
information, and the lower 32 bits are nanosecond-level time information.
PTP reference clock input is used to generate the system reference time (referred to as the system time) and obtain
the timestamp value of PTP frame. PTP reference clock frequency cannot be less than the resolution of the timestamp
counter, and the time synchronization accuracy between the master node and the slave node is about 0.1us.
Synchronization accuracy
The accuracy of time synchronization depends on the frequency of PTP reference clock input and the frequency drift
characteristics of the crystal oscillator used, as well as how often the synchronization process is performed.
System time calibration method
The 64-bit PTP system time is used as the basis for recording send/receive timestamps, and is updated by PTP input
reference clock. In order to correct the frequency offset, PTP system time needs to be calibrated, and the initialization
and calibration support two modes of coarse adjustment and fine adjustment.
Rough Adjustment Calibration Perform system time initialization and calibration by configuring the PTP timestamp
update registers (ETH_PTPSECUP and ETH_PTPNSUP). If ETH_PTPTSCTRL.TSINIT is set, the PTP timestamp
update register is used for initialization; if ETH_PTPTSCTRL.TSUPDT is set, the system time plus or minus the
value of PTP timestamp update register is used to adjust the system time.
Fine-tuning calibration is to add the value in the addend register ETH_PTPTSADD to the accumulator every HCLK
cycle. A pulse is generated when the accumulator overflows, causing the value of the timestamp low register
ETH_PTPSS to increment according to the value of the subsecond increment register ETH_PTPSSINC. This process
needs to wait for a period of time to complete, to ensure that the slave clock can be linearly synchronized with the
master clock to avoid large jitter.
The following diagram illustrates the flow of the fine-tuning algorithm:
