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/
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Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
This bit indicates the level of the VSYNC pin when there is valid data on the parallel
interface.
0: VSYNC active low
1: VSYNC active high
2
HSPOL
Horizontal sync polarity.
This bit indicates the level of the HSYNC pin when there is valid data on the parallel
interface.
0: HSYNC active low
1: HSYNC active high
1
CM
capture mode.
0: Single frame mode. Once activated, the interface waits for the frame sync signal to
be valid, and then starts transmitting data. After a frame of data is transmitted, the
CAPTURE bit is automatically cleared.
1: Continuous mode. After transmitting a frame of data, the CAPTURE bit is not
cleared and continues to wait for the next frame synchronization signal.
0
CAPTURE
Capture enable.
In single frame mode, this bit is automatically cleared to 0 after the first frame is
received. In continuous mode, it needs to be cleared by software. If the software
clears 0 while the capture is in progress, this bit is not cleared until the current frame
is captured.
0: Disable capture function
1: Enable capture function
Note: Before enabling capture, the DMA controller and DVP configuration registers
must be properly configured as required.
28.4.3
DVP Status Register
（
DVP_STS
）
Address offset : 0x04
Reset value : 0x0000 0000
Bit field
Name
Description
31:4
Reserved
Reserved, the reset value must be maintained.
3:1
FCNT[2:0]
Length of data in FIFO.
0
FNE
FIFO not empty flag.
0: FIFO is empty
1: There is valid data in the FIFO
