753
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
These bits are the lower 32 bits of the HASH list.
25.5.6
ETH MAC MII address register (ETH_MACMIIADDR)
Address offset: 0x0010
Reset value: 0x0000 0000
This register controls the management signals of the external PHY through the interface.
Bit field
Name
Description
31:16
Reserved
Reserved, the reset value must be maintained.
15:11
PA[4:0]
PHY address.
These bits represent the accessed PHY address.
10:6
MR[4:0]
MII PHY registers.
These bits select the PHY register to be accessed.
5
Reserved
Reserved, the reset value must be maintained.
4:2
CR[2:0]
Clock range.
These bits are used to configure the clock of MDC according to the frequency of
HCLK.
value
MDC frequency
HCLK frequency
000
HCLK/42
60~100MHz
001
HCLK/62
100~144MHz
010
HCLK/16
20~35MHz
011
HCLK/26
35~60MHz
other
Reserved
Reserved
1
MW
MII write operation.
0: Read the PHY.
1: Write to PHY.
0
MB
MII busy.
This bit should be 0 before writing to register ETH_MACMIIADDR and
ETH_MACMIIDAT. When accessing the PHY, this bit is set by the application
program to indicate that a read or write operation is being performed on the PHY.
When writing to the PHY, the value of the ETH_MACMIIDAT register must be
retained until this bit is cleared by hardware. When the PHY is read, the value of the
ETH_MACMIIDAT register is valid after the hardware clears this bit.
