Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
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+86-755-86309900
Email
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info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit Field Name Description
The hardware updates this bit after each sending attempt of mailbox 1:
0: The last sending attempt is not yet successful;
1: The last sending attempt was successful.
When the sending request of mailbox 1 is successfully completed, the hardware
sets this bit. See Figure 20-7.
8 RQCPM1 Request completed mailbox 1
When the last request (send or abort) for mailbox 1 is completed, the hardware
sets this bit.
Writing '1' to this bit by software can clear it; When the hardware receives the
send request, it can also clears this bit (the CAN_TMI1.TXRQ bit is set).
When this bit is cleared, other sending status bits (CAN_TSTS.TXOKM1,
CAN_TSTS.ALSTM1 and CAN_TSTS.TERRM1 bits) of mailbox 1 are also
cleared.
7 ABRQM0 Abort request for mailbox 0
The software can stop the sending request of mailbox 0 by setting this bit , and the
hardware clears this bit when the sending message of mailbox 0 is idle. If there is
no message waiting to be sent in mailbox 0, it will have no effect to set this bit.
6:4 Reserved Reserved, the reset value must be maintained.
3 TERRM0 Transmission error of mailbox 0
When the mailbox 0 fails to send due to an error, set this bit.
2 ALSTM0 Arbitration lost for mailbox 0
When the mailbox 0 fails to send due to the loss of arbitration, set this bit
1 TXOKM0 Transmission OK of mailbox 0
The hardware updates this bit after each attempt to send mailbox 0:
0: The last send attempt is not yet successful;
1: The last sending attempt was successful.
When the sending request of mailbox 0 is successfully completed, the hardware
sets this bit. See Figure 20-7.
0 RQCPM0 Request completed mailbox 0
When the last request (send or abort) for mailbox 0 was completed, the hardware
sets this bit.
Writing '1' to this bit by software can clear it; When the hardware receives the
send request, it can also clears this bit (the CAN_TMI0.TXRQ bit is set).
When this bit is cleared, other sending status bits (CAN_TSTS.TXOKM0,
CAN_TSTS.ALSTM0 and CAN_TSTS.TERRM0 bits) of mailbox 0 are also
cleared.
CAN receive FIFO 0 register (CAN_RFF0)
Address offset: 0x0c
Reset value: 0x0000 0000