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Send mailbox x becomes empty, and the corresponding CAN_TSTS.RQCPMx bit is set(x=1/2/3).
Error and status change interrupt
(CAN_SCE_IRQn):
CAN enters sleep mode;
Wake-up condition, the start of frame bit (SOF) is monitored on the CAN receiving pin.
Error condition, please refer to the CAN error status register (CAN_ESTS) for details of the error.
20.5.1
Error management
As described in CAN protocol, the error management is completely realized by hardware through sending error
counter (CAN_ESTS.TXEC field) and receiving error counter (CAN_ESTS.RXEC field). The counter value will
increase or decrease according to the error situation. Please refer to CAN standard if you want to know more detailed
information about CAN_ESTS.TXEC and CAN_ESTS.RXEC management.
Figure 20-14 CAN error state diagram
Software can read out the value of the sending/receiving error counter to judge the stability of CAN network, and
CAN_ESTS.LEC[2:0] bits can be read to get the detailed information of the current error status. What’s more, by
setting the CAN_INTE register (such as CAN_INTE. LECITE bit), the software can flexibly control the generation
of interrupts when an error is detected.
20.5.2
Bus-Off recovery
When TXEC is greater than 255, the CAN_ESTS.BOFFL bit is set indicating that CAN goes bus-off. at this time,
CAN can't receive and send messages.
In normal mode, according to the CAN_MCTRL.ABOM bit, CAN can automatically or at the request of software,
recover from bus-off state, and change to error active state. If the CAN_MCTRL.ABOM bit is set, the recovery
process will be started automatically after it has entered bus-off state. Otherwise, the recovery process will be started
after software must request CAN to enter and then exit initialization mode. In both cases, CAN must wait for a
recovery process described in CAN standard, that is 128*11 consecutive recessive bits are detected on CAN RX pin.
In initialization mode, CAN will not monitor the status of CAN RX pin, so the recovery process cannot be completed.
CAN Configuration Flow
This chapter will introduce common configuration procedure of CAN while other details like functions of each mode
and register bits are revealed in other part of this manual. CAN configuration flow can divided into serval phases.
Error Active
Error Passive
Bus off
Reset
TXEC or
RXEC>127
TXEC and
RXEC<128
TXEC > 255
When 128*11 recessive bits occur
