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Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
1110
3.42v
1111
3.60v
8
DBKP
Cancel the write protection of the backup power domain.
In the reset state, the RTC and backup domain registers should be protected to
prevent illegal writing. This bit must be set to enable write access to these registers.
0: Disable access to RTC and backup registers
1: Enable access to RTC and backup registers
Note: This bit must remain 1 if the RTC clock is HSE/128.
7:5
PRS[2:0]
PVD monitoring voltage selection.
Combinations of different bits represent different voltage thresholds of the voltage
detector.
These bits need to be configured in conjunction with the MSB bit. For specific voltage
thresholds, see the description of the MSB bit.
NOTE: See the Electrical Characteristics section in the datasheet for detailed
descriptions.
4
PVDEN
Power supply voltage monitor (PVD) enabled.
0: Disable PVD
1: Enable PVD
3
CSBVBAT
Clear STANDBY/VBAT bit.
always reads as 0
0: invalid
1: Clear PWR_CTRLSTS.SBF and PWR_CTRLSTS.VBATF standby bits (write)
2
CWKUP
Clear wakeup bit.
always reads as 0
0: invalid
1: Clear PWR_CTRLSTS.WKUPF wake-up bit after 2 system clock cycles (write)
1
PDS
Power-down deep-sleep bit.
Operates in conjunction with the LPS bit
0: Enters shutdown mode when the CPU enters deep sleep, the state of the voltage
regulator is controlled by the LPS bit.
1: Enter standby mode when the CPU enters deep sleep.
0
LPS
Low power consumption in deep sleep.
When PDS=0, cooperate with the PDS bit
0: Voltage regulator on in shutdown mode
1: Voltage regulator in low power mode in shutdown mode
4.4.3
Power control status register(PWR_CTRLSTS)
Address offset: 0x04
Reset value: 0x0000 0000 (not cleared when waking up from standby mode)
