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Nations Technologies Inc.
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The backup domain reset is generated when one of the following events occurs:
Software reset: The backup domain reset can be generated by setting the RCC_BDCTRL.BDSFTRST bit.
Under the premise that both VDD and VBAT are powered off, the backup area will be reset only when VDD or
VBAT is powered on
.
Clock control unit
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock;
HSE oscillator clock;
PLL clock;
The devices have the following two secondary clock sources:
LSI: 40 kHz low-speed internal RC which drives independent watchdog (IWDG) can be selected by software to
drive RTC. RTC is used to automatically wake up the system from STOP0/STOP2/STANDBY mode.
LSE: 32.768 kHz low-speed external crystal can also be selected by software to drive RTC(RTCCLK).
Each clock source can be turned on or off independently when it is not used to optimize power consumption.
Several prescalers can be used to configure the frequencies of the AHB, the high-speed APB (APB2), and the low-
speed APB (APB1) domains. The maximum frequencies of the AHB, APB2, and APB1 domains are 144MHz,
72MHz, and 36MHz respectively. The clock frequency of the SDIO interface is fixed at HCLK/2.
RCC provides the Cortex System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. This
clock or Cortex clock(HCLK) can be selected to drive the SysTick by programming the SysTick Control and Status
Register. The ADC clock is generated by dividing the AHB clock or PLL clock.
The clock frequencies of timers are automatically set by hardware. There are two scenarios:
If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain
to which the timers are connected.
Otherwise, they are set to twice the frequency of the APB domain to which the timers are connected.
FCLK is the free-running clock of Cortex™-M4F. For more details, refer to the ARM Cortex™-M4 technical
reference manual.
