400
/
838
Nations Technologies Inc.
Tel
:
+86-755-86309900
:
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Alarm clock output (polarity configurable), Alarm A and Alarm B are optional.
Auto wakeup output (polarity configurable).
RTC input functions:
Timestamp event detection
Control PC13 by configuring output register:
Set RTC_OPT.TYPE bit to configure open-drain/push-pull output of PC13
14.2.2
GPIOs of RTC
Timestamp input come from IOM (mapped to PC13) or EXTI module, if EXTI module is needed to start, please refer
to the timestamp trigger source selection register (EXTI_TS_SEL) for details.
RTC_OUT (Alarm, Wakeup event or calibration output (256Hz or 1Hz)) is mapped to PC13. Regardless of the PC13
GPIO configuration, the PC13 pin configuration is controlled by the RTC as an output.
14.2.3
RTC register write protection
PWR_CTRL.DBKP bit (see the Power Control section) is cleared in default, so the PWR_CTRL.DBKP bit must set
to “1” to enable write access to the RTC register. Once the backup domain is reset, all write protection RTC registers
are write protected. All write protection RTC registers require the following steps to unlock write protection:
Write “0xCA” into RTC_WRP register.
Write “0x53” into RTC_WRP register.
The unlocking mechanism only checks the write operation to the RTC_WRP register. During or before and after the
unlocking process, the write operation to other registers does not affect the unlocking result.
14.2.4
RTC clock and prescaler
RTC clock source:
LSE clock
LSI clock
HSE/128 clock
For the purpose of reduction of power consumption, the prescaler is divided into 2 programmable prescalers, they
are asynchronous prescaler and synchronous prescaler. If both prescaler are used, it is recommended that the value
of the asynchronous divider be as large as possible.
A 7-bit asynchronous prescaler which is given by RTC_PRE.DIVA[6:0] bits
A 15-bit synchronous prescaler which is given by RTC_PRE.DIVS[14:0] bits
The formula for f
ck_apre
and f
ck_spre
are given below:
f
ck_apre
=
𝑓
𝑅𝑇𝐶𝐶𝐿𝐾
𝑅𝑇𝐶_𝑃𝑅𝐸.𝐷𝐼𝑉𝐴[6:0]+1