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and transmitter should update the I2C_DAT register at the specified time according to the I2C bus standard.
In sending the first byte, I2C_DAT register must be written after I2C_STS1.ADDRF bit is cleared and the before the
first SCL rising edge. If cannot make sure do that, the first byte should be discard by receiver.
22.3.4
DMA application
DMA can generate a requests when transfer data register empty or full. DMA can oprate write data to I2C or read
data from I2C reduce burden of CPU.
Before transfer current byte at the end DMA requests must be answered. If set the DMA channel transfer data is done,
DMA will send EOT(End Of Transmission) to I2C, and ocurrs a interrupt when enable interrupt bit.
In the master transfer mode, in EOT interrupt handler DMA request need to be disbale, and set stop condition after
waiting for I2C_STS1.BSF event.
In the master receive mode, the data of received is great than or equal to 2, DMA will send a hardware signal EOT_1
in DMA transmission(byte number-1). If set I2C_CTRL2.DMALAST bit, when hardware have send the EOT_1 next
byte it will send a NACK automatically. The user can set a stop condition in the interrupt handler after the DMA
transfer is completed if interrupt enable.
Note: When I2C and other peripherals use the same DMA controller, they cannot be turned on at the same time.
Transmit process
If use the DMA mode need set the I2C_CTRL2.DMAEN bit. When I2C_STS1.TXDATE bit is set, the data will send
to I2C_DAT from storage area by the DMA. DMA assign a channle for I2C transmission, (x is the channel number)
the following step must be opreate:
1.
In the DMA_PADDRx register set the I2C_DAT register address. Data will be send to address in every
I2C_STS1.TXDATE event.
2.
In the DMA_MADDRx register set the memory address. Data will send to I2C_DAT address in every
I2C_STS1.TXDATE event.
3.
In the DMA_TXNUMx register set the number of need to be transferred.In every I2C_STS1.TXDATE event
this number-1 until 0.
4.
In the DMA_CHCFGx register set PRIOLVL[1:0] bit to configure the priority of channel.
5.
In the DMA_CHCFGx register set DIR bit to configure when ocurrs an interrupt whether send a half data or all
completed.
6.
In the DMA_CHCFGx register set CHEN bit to enable transfer channel.
7.
When DMA transfer data is done, DMA need send a EOT/EOT_1 signal to I2C indicate this transfer is done. If
interrupt is enable, DMA ocurrs a interrrupt.
Note: if DMA is used for transmission, do not set I2C_CTRL2.BUFINTEN bit.
Receive process
If use DMA mode need set I2C_CTRL2.DMAEN bit. When data byte is received,DMA will send I2C data to storage
area, set DMA channel for I2C reception. The following steps must be opreate:
