Nations N32G45 Series, User Manual

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584 / 838
Nations Technologies Inc.
Tel
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+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
21.3.7 Error flag
Master mode failure error (MODERR)
The following two conditions will cause the master mode failure error:

NSS pin hardware management mode, the master device NSS pin is pulled low;

NSS pin software management mode, the SPI_CTRL1.SSEL bit is set to 0.
When a master mode failure error occurs, the SPI_STS.MODERR bit is set to 1. An interrupt is generated if the user
enables the corresponding interrupt (SPI_CTRL2.ERRINTEN = 1). The SPI_CTRL1.SPIEN bit and
SPI_CTRL1.MSEL bit will be write protected and both are cleared by hardware. SPI is turned off and forced into
slave mode
Software performs a read or write operation to the SPI_STS register, and then writes to the SPI_CTRL1 register to
clear the SPI_STS.MODERR bit (in multi-master mode, the master's NSS pin must be pulled high first).
Normally, the SPI_STS.MODERR bit of the slave cannot be set to 1. However, in a multi-master configuration, the
slave's SPI_STS.MODERR bit may be set to 1. In this case, the SPI_STS.MODERR bit indicates that there is a multi-
master collision. The interrupt routine can perform a reset or return to the default state to recover from an error state.
Overflow error (OVER)
When the SPI_STS.RNE bit is set to 1, but there is still data sent into the receive buffer, an overflow error will occur.
At this time, the overflow flag SPI_STS.OVER bit is set to 1. An interrupt is generated if the user enables the
corresponding interrupt (SPI_CTRL2.ERRINTEN = 1). All received data is lost, and the SPI_DAT register retains
only previously unread data.
Read the SPI_DAT register and the SPI_STS register in turn to clear the SPI_STS.OVER bit.
CRC error (CRCERR)
The CRC error flag is used to check the validity of the received data. A CRC error occurs when the received CRC
value does not match the SPI_CRCRDAT value. At this time, the SPI_STS.CRCERR flag bit is set to '1', and an
interrupt will be generated if the user enables the corresponding interrupt (SPI_CTRL2.ERRINTEN = 1).
21.3.8 SPI interrupt
Table 21-1 SPI interrupt request
Interrupt event Event flag bit Enable control bit
Send buffer empty flag TE TEINTEN
Receive buffer non empty flag RNE RNEINTEN
Master mode failure event MODERR
ERRINTEN Overflow error OVER
CRC error flag CRCERR