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Nations Technologies Inc.
Tel
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+86-755-86309900
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
0: CAN1 is still running normally;
1: The receiving register of CAN1 does not continue to receive data
13:10
TIMx_STOP
When the kernel enters the debugging state, the counter stops working (x=4,3,2,1).
Set or cleared by software.
0: The counter of the selected timer still works normally;
1: The counter of the selected timer stops working.
9
WWDG_STOP
When the kernel enters the debug state, the debug window watchdog stops
working.
Set or cleared by software.
0: The window watchdog counter still works normally;
1: Window watchdog counter stops working.
8
IWDG_STOP
The watchdog stops working when the kernel enters the debugging state.
Set or cleared by software.
0: Watchdog counter still works normally;
1: Watchdog counter stops working.
7:3
Reserved
Reserved, must keep the reset value.
2
STDBY
Debug standby mode.
Set or cleared by software.
0: (FCLK OFF, HCLK OFF) The whole digital circuit is powered off. From the
software point of view, exiting the STANDBY mode is the same as resetting
(except that some status bits indicate that the microcontroller has just exited from
the STANDBY state).
1: (FCLK ON, HCLK ON) The digital circuit part is not powered down, and the
FCLK and HCLK clocks are clocked by the internal RLD oscillator. In addition, it
is the same as resetting that the microcontroller exits the STANDBY mode by
generating a system reset.
1
STOP
Debug stop mode.
Set or cleared by software.
0: (FCLK OFF, HCLK OFF) In stop mode, the clock controller disables all clocks
(including HCLK and FCLK). When exiting from STOP mode, the configuration of
the clock is the same as that after reset (the microcontroller is clocked by the 8MHz
internal RC oscillator (HSI)). Therefore, the software must reconfigure the clock
control system to start PLL, crystal oscillator, etc.
1: (FCLK ON, HCLK ON) In stop mode, the FCLK and HCLK clocks are provided
by the internal RC oscillator. When exiting the stop mode, the software must
reconfigure the clock system to start PLL, crystal oscillator, etc. (the same
operation as when this bit is set to 0).
0
SLEEP
Debug sleep mode.
Set or cleared by software.
0: (FCLK is ON, HCLK is OFF) In sleep mode, FCLK is provided by the
previously configured system clock, while HCLK is off. Since sleep mode does not
reset the configured clock system, the software does not need to reconfigure the
