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Nations Technologies Inc.
Tel
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+86-755-86309900
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
External clock mode 2 is selected by setting TIMx_SMCTRL .EXCEN equal to ‘1’
Turn on the counter by setting TIMx_CTRL1. CNTEN equal to ‘1’
The counter counts every 2 rising edges of ETR. The delay between the rising edge of ETR and the actual clock to
the counter is due to a resynchronization circuit on the ETRP signal.
Figure 11-15 Control circuit in external clock mode 2
11.3.5
Capture/compare channels
Capture/compare channels include capture/compare registers and shadow registers. The input section consists of
digital filters, multiplexers and prescalers. The output section includes comparators and output controls.
The input signal TIx is sampled and filtered to generate the signal TIxF. A signal (TIxF_rising or TIxF_falling) is
then generated by the edge detector of the polarity select function, the polarity of which is selected by the
TIMx_CCEN.CCxP bits. This signal can be used as a trigger input for the slave mode controller. At the same time,
the signal ICx is sent to the capture register after frequency division. The following figure shows a block diagram of
a capture/compare channel.
Counter clock = CK_CNT=CK_PSC
CNTEN
ETR
Counter register
34
35
36
f
CK _INT
ETRP
ETRF
