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Nations Technologies Inc.
Tel
:
+86-755-86309900
:
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 21-3 Master and slave applications
Note: NSS pin is set as input
SPI is a ring bus structure. The master device outputs a synchronous clock signal through the SCK pin, the MOSI pin
of the master device is connected to the MOSI pin of the slave device, and the MISO pin of the master device is
connected to the MISO pin of the slave device, so that data can be transferred between devices. Continuous data
transfer between master and slave, sending data to slave through MOSI pin and slave sending data to master through
MISO pin.
SPI timing mode
User can selects the clock edge of data capture by setting SPI_CTRL1.CLKPOL bit and SPI_CTRL1.CLKPHA bit.
When CLKPOL = 0, CLKPHA = 0, the SCLK pin will keep low in idle state, and the data will be sampled at
the first edge, which is rising edge.
When CLKPOL = 0, CLKPHA = 1, the SCLK pin will keep low in idle state, and the data will be sampled at
the second edge, which is falling edge.
When CLKPOL = 1, CLKPHA = 0, the SCLK pin will keep high in idle state, and the data will be sampled at
the first edge, which is falling edge.
When CLKPOL = 1, CLKPHA = 1, the SCLK pin will keep high in idle state, and the data will be sampled at
the second edge, which is rising edge.
Regardless of the timing mode used, the master and slave configuration must be the same.
Figure 21-4 is the combination timing of four CLKPHA and CLKPOL bits transmitted by SPI when the
SPI_CTRL1.LSBFF = 0.
8-bit shift register
SPI clock
generator
8-bit shift register
MSBit
Not used if NSS is managed
by software
Master
Slave
MISO
MOSI
SCK
NSS(1)
LSBit
MSBit
LSBit
NSS(1)
VDD