706
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Set timestamp of received frame and transmitted frame
Support two calibration methods: rough adjustment and fine adjustment
Interrupt can be triggered when the system time reaches a predetermined time
Output second pulse
Function block diagram
Ethernet peripheral mainly includes MAC module, MII/RMII interface module and a DMA module controlled in the
form of descriptor. MAC module is connected to the off-chip PHY device through MII or RMII. MII or RMII
connection method must be selected by software configuration AFIO_RMP_CFG.MII_RMII_SEL before the
Ethernet controller enables the clock or in the reset state. The default configuration is MII mode. SMI interface for
configuring and managing external PHY devices.
Ethernet DMA controller accesses the MAC controller through the AHB master interface to control data transfer;
accesses the MAC memory through the slave interface to access the control and status register areas.
Before the MAC controller sends data, the Ethernet DMA will first read the data from the system memory area and
store it in the TxFIFO. The Ethernet frame received by the MAC controller from the bus will be first buffered in the
RxFIFO, and then transferred to the system storage area by the Ethernet DMA.
Figure 25-1 Ethernet Module Block Diagram
Function description
25.4.1
IEEE 802.3 ethernet frame format
There are two frame formats for the data communication of the MAC compliant with the IEEE 802.3-2008 standard:
AHB
Arbitration
ETH
DMA
TxFIFO(2K)
RxFIFO(2K)
MAC
S
e
le
ct
P
H
Y
PTP
AHB
m
as
te
r
in
te
rf
ac
e
AHB
s
la
v
e
in
te
rf
ac
e
Operation
Mode
Register
DMA Control
and Status
Register
MMC
PMT
Check
