741
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 25-9 System time precision calibration
The following example illustrates the configuration method of updating system time in fine adjustment mode:
Set the initial value of the addend register (Clock_Addend_Value(0)) to the slave clock, the initial value is calculated
in the following way: The accuracy of the system clock update circuit needs to reach 20ns (the update frequency is
50MHz). When the reference clock HCLK is 70MHz, the frequency ratio is 70/50 = 1.4, the addend that should be
written into the ETH_PTPTSADD register is 2
32
/1.4 = 0xB6DB 6DB6; when the frequency drift of the reference
clock is reduced to 60MHz, the frequency ratio becomes 60/50 = 1.2, and the addend written to the addend register
is the value should be 2
32
/1.2 = 0xD555 5555; when the base clock frequency drift increases to 80MHz, the frequency
ratio becomes 80/50 = 1.6, and the value written to the addend register should be 2
32
/1.6 = 0xA000 0000. After
configuring the up-counter, it is necessary to configure the sub-second increment register to ensure the accuracy of
20ns. The value of the subsecond increment register updates the timestamp low register each time the accumulation
register overflows. Since bits 0 to 30 of the timestamp low register represent the sub-second value of the system time,
the precision is equal to 10
9
ns/2
31
= 0.46ns. In order to achieve a system time accuracy of 20ns, the value of the sub-
second increment register should be set to 20/0.46 = 43.
Assuming that the delay Master_to_Slave_Delay transmitted between the master and slave devices is a fixed value,
the time when the master device sends a SYNC message to the slave device is MSYNCT(n), the local time of the
slave device is SLOCALT(n), and the local time of the master device is MLOCALT(n), the master clock count
between two SYNC messages is MCLOCKC(n), the slave clock count between two SYNC messages is
SCLOCKC(n), and the slave clock frequency adjustment factor is SCFAF(n) ), the clock addend value of the addend
register is Clock_Addend_Value(n), then the calculation method to determine the synchronization frequency in
multiple SYNC cycles is as follows, but note that multiple SYNC messages may be required to complete the
synchronization of the master and slave devices according to the situation:
MLOCALT(n) = MSYNCT(n) + Master_to_Slave_Delay(n)
MCLOCKC(n) = MLOCALT(n) - MLOCALT(n-1)
SCLOCKC(n) = SLOCALT (n) - SLOCALT(n-1)
SCFAF(n) = (MCLOCKC(n) + MCLOCKC(n) - SCLOCKC(n)) / SCLOCKC(n)
Clock_Addend_Value(n) = SCFAF(n) * Clock_Addend_Value(n-1)
System time initialization process
Timestamp function needs to configure ETH_PTPTSCTRL.TSENA to 1 first, and then initialize timestamp counter
Addend
register
+
Accumul
-ator
register
Constant
value
Subsecond
register
+
Seconds
register
Updated
addend
Increment
subsecond register
Increment
seconds
register
