Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Table 21-2 Use the standard 8MHz HSE clock to get accurate audio frequency.
SYSCLK
（
MHz
）
I
2
S_LDIV I
2
S_ODD_EVEN
MCLK
Target
F
S
(Hz)
Real F
S
(Hz) Error
16 bits 32 bits 16 bits 32 bits 16 bits 32 bits 16 bits 32 bits
72 11 6 1 0 without 96000 97826.09 93750 1.90% 2.34%
72 23 11 1 1 without 48000 47872.34 48913.04 0.27% 1.90%
72 25 13 1 0 without 44100 44117.65 43269.23 0.04% 1.88%
72 35 17 0 1 without 32000 32142.86 32142.86 0.44% 0.44%
72 51 25 0 1 without 22050 22058.82 22058.82 0.04% 0.04%
72 70 35 1 0 without 16000 15675.75 16071.43 0.27% 0.45%
72 102 51 0 0 without 11025 11029.41 11029.41 0.04% 0.04%
72 140 70 1 1 without 8000 8007.11 7978.72 0.09% 0.27%
72 2 2 0 0 yes 96000 70312.15 70312.15 26.76% 26.76%
72 3 3 0 0 yes 48000 46875 46875 2.34% 2.34%
72 3 3 0 0 yes 44100 46875 46875 6.29% 6.29%
72 4 4 1 1 yes 32000 31250 31250 2.34% 2.34%
72 6 6 1 1 yes 22050 21634.61 21634.61 1.88% 1.88%
72 9 9 0 0 yes 16000 15625 15625 2.34% 2.34%
72 13 13 0 0 yes 11025 10817.3 10817.3 1.88% 1.88%
72 17 17 1 1 yes 8000 8035.71 8035.71 0.45% 0.45%
21.4.3 I
2
S Transmission and reception sequence
I
2
S initialization sequence
1. The user can set the SPI_I2SPREDIV.LDIV [7:0] bits and SPI_I2SPREDIV.ODD_EVEN bit to configure the
related prescaler and serial clock baud rate;
2. If the user needs the master device to provide the main clock MCLK to the external DAC/ADC audio device, set
the SPI_I2SPREDIV.MCLKOEN = 1. (Calculate LDIV and ODD_EVEN according to different clock outputs,
see section 21.4.2).
3. The user can set the SPI_I2SCFG.CLKPOL bit to define the polarity of the communication clock when idle; the
user can set the SPI_I2SCFG.MODSEL = 1 to configure the device to be in I2S mode, and set
SPI_I2SCFG.MODCFG[1:0] bits to select the I2S master-slave mode and transmission direction (send or
receive); set SPI_I2SCFG.STDSEL[1:0] bits to select the corresponding I2S standard (under the PCM standard,
set the SPI_I2SCFG.PCMFSYNC bit to select the PCM frame synchronization mode); set
SPI_I2SCFG.TDATLEN [1:0] bits to select length of data to be transmitted, and select the number of data bits
of per channel by set the SPI_I2SCFG.CHBITS bit;
4. When user needs to enable interrupt or DMA, the configuration operation is the same as SPI;
5. Finally, set the SPI_I2SCFG.I2SEN = 1 to start I2S communication.
Sending sequence
Master mode
When I2S works in master mode, the CLK pin outputs the serial clock, the WS pin generates the channel selection