195
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0A8h
DMA_CHMAPEN
Reserved
M
AP_E
N
Reset Value
0
8.5.2
DMA interrupt status register (DMA_INTSTS)
Address offset: 0x00
Reset value: 0x0000 0000
Bit field
Name
Description
31/27/23/19/15/11/7/3
ERRFx
Transfer error flag for channel x (x=1…8).
Hardware sets this bit when transfer error happen. This bit is cleared by software by
writing ‘1’ to DMA_INTCLR.CERRFx bit.
0: Transfer error no happened on channel x.
1: Transfer error happened on channel x.
30/26/22/18/14/10/6/2
HTXFx
Half transfer flag for channel x (x=1…8).
Hardware sets this bit when half transfer is done. This bit is cleared by software by
writing ‘1’ to DMA_INTCLR.CHTXFx bit.
0: Half transfer not yet done on channel x.
1: Half transfer was done on channel x.
29/25/21/17/13/9/5/1
TXCFx
Transfer complete flag for channel x (x=1…8).
Hardware sets this bit when transfer is done. This bit is cleared by software by writing
‘1’ to DMA_INTCLR.CTXCFx bit.
0: Transfer not yet done on channel x.
1: Transfer was done on channel x.
28/24/20/16/12/8/4/0
GLBFx
Global flag for channel x (x=1…8).
Hardware sets this bit when any interrupt events happen in this channel. This bit is
cleared by software by writing ‘1’ to DMA_INTCLR.CGLBFx bit.
0: No transfer error, half transfer or transfer done event happen on channel x.
1: One of transfer error, half transfer or transfer done event happen on channel x.
8.5.3
DMA interrupt flag clear register (DMA_INTCLR)
Address offset: 0x04
Reset value: 0x0000 0000
