Nations N32G45 Series, User Manual

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Nations Technologies Inc.
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+86-755-86309900
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info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
The HSI frequency can be trimmed by using the RCC_CTRL.HSITRIM[4:0] bits.
The RCC_CTRL.HSIRDF bit flag indicates if the HSI RC oscillator is stable. At startup, the HSI RC output clock is
not released until this bit is set by hardware. HSI clock can be switched on and off using the RCC_CTRL.HSIEN bit.
If the HSE crystal oscillator fails, the HSI clock is used as a backup clock source. Refer to Section 6.2.8 Clock
Security System.
6.2.4 PLL clock
The internal PLL can be used to multiply the HSI or the HSE clock frequency. Refer to Figure 6-2 Clock Tree,The
PLL configuration (selection of PLL input clock (HSI/HSE and divider) and multiplication factor) must be done
before enabling PLL. Once the PLL is enabled, these parameters cannot be changed. The PLL can be configured
using control bits in RCC_CTRL and RCC_CFG registers.
If the PLL interrupt is enabled in the clock interrupt register, an interrupt request can be generated when the PLL is
ready.
If the USB interface needs to be used in the application, the PLL must be set to output 48, 72, 96,144MHz clocks to
provide the 48MHz USBCLK clock.
6.2.5 LSE clock
The LSE crystal is a 32.768KHz low speed external crystal or ceramic resonator. It provides a low-power and accurate
clock source for the real-time clock or other timing functions.
The LSE clock is enabled and disabled by the RCC_BDCTRL.LSEEN bit.
The RCC_BDCTRL.LSERD bit indicates whether the LSE clock is stable. During the startup phase, the LSE clock
signal is not released until this bit is set by hardware. If enabled in the clock interrupt register, an interrupt request
can be generated.
LSE external clock source(LSE bypass)
In this mode, an external clock source with a frequency of up to 1 MHz can be provided. Users can select this mode
by setting the RCC_BDCTRL.LSEBP and RCC_BDCTRL.LSEEN bits. The external clock signal(square, sine or
triangle wave) with 50% duty cycle must be connected to the OSC32_IN pin while the OSC32_OUT pin must be left
floating (Hi-Z).
6.2.6 LSI clock
The LSI RC can clock the IWDG and AWU in STOP0/STOP2 and STANDBY modes. The LSI clock frequency is
about 40kHz. For further information please refer to the Electrical Characteristics section of the data sheet.
The LSI clock can be turned on or off using the RCC_CTRLSTS.LSIEN bit.
The RCC_CTRLSTS.LSIRD bit flag indicates if the LSI clock is stable. At startup, the clock is not released until this
bit is set by hardware. An interrupt can be generated if enabled in the Clock Interrupt Register (RCC_CLKINT).