779
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
31:0
STL[31:0]
Transmit queue base address.
These bits contain the address of the first descriptor of the transmit descriptor queue.
TxDMA ignores the lowest 2 bits and defaults to 0.
25.5.47
ETH DMA status register (ETH_DMASTS)
Address offset: 0x1014
Reset value: 0x0000 0000
This register contains all the status bits that the DMA feeds back to the application. Software usually reads this
register in an interrupt service routine or during polling. Most bits in this register can trigger interrupts. Reading this
register does not clear the flags in it. Writing 1 to bit0~bit16 (except reserved bits) can clear them, while writing 0 is
invalid. By setting the corresponding bits in the ETH_DMAINTEN register, the interrupts triggered by these bits
(except reserved bits) of bit0~bit16 can be masked.
Bit field
Name
Description
31:30
Reserved
Reserved, the reset value must be maintained.
29
TTI
Timestamp trigger status.
This bit indicates that a timestamp interrupt event has occurred. Clear this bit by
clearing ETH_MACINTSTS.TSTS. When this bit is set to 1, an interrupt is generated
if the corresponding interrupt is enabled.
0: No timestamp interrupt event occurred.
1: A timestamp interrupt event has occurred.
28
PMTI
PMT status.
This bit indicates that an interrupt event has occurred in the PMT module of the MAC
controller. Software must read the corresponding register of the MAC controller, find
the source of the interrupt and clear it, in order to clear this bit. When this bit is set, an
interrupt is generated if the corresponding interrupt is enabled.
0: No PMT interrupt event occurred.
1: A PMT interrupt event has occurred.
