Nations N32G45 Series, User Manual

Page: 205 / 838

205 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China

Support DMA.

Interrupt generation.

At the end of conversion.

At the end of injection conversion.

Analog watchdog event.

Data alignment with embedded data consistency.

Both regular conversions and injection conversions have external triggering options.

ADC power requirements: 1.8V to 3. 6V.

ADC input voltage range: V
REF
- ≤ V
IN
≤ V
REF+.

Dual ADC mode, ADC1 and ADC2 combined, ADC3 and ADC4 combined.
Function Description
The block diagram and pin description of the ADC are as follows:
Figure 9-1 Block diagram of a single ADC
V
REF +
V
REF -
V
DDA
V
SSA
Injected
channels
Regular
channels
Analog to
digital
channels
ADCx_IN1
ADCx_IN2
ADCx_IN15
Gpio
Ports
A
n
a
lo
g
c
h
a
n
n
e
l
m
u
lt
ip
le
x
in
g
V
TS
V
REFINT
ADCCLK
ADC prescaler
Data bus
Injected data registers
(4 x 16 bits)
Regular data register
(16 bits)
Data register
Analog
watchdog
Interrupt
generate
Analog watchdog event
End of injected conversion
End of conversion
ADC Interrupt to NVIC
DMA request
A
D
C
_
C
T
R
L
2
.
E
X
T
J
T
R
IG
b
it
T
IM
1
_
T
R
G
O
T
IM
1
_
CH
4
T
IM
2
_
T
R
G
O
T
IM
2
_
CH
1
T
IM
4
_
T
R
G
O
T
IM
3
_
CH
4
T
IM
8_
CH
4
E
X
T
I_
15
AFIO_RMP_CFG.
ADCx_ETRI bit
A
D
C
_
C
T
R
L
2
.
E
X
T
R
T
R
IG
b
it
T
IM
8_
T
R
G
O
AFIO_RMP_CFG.
ADCx_ETRR bit
ADC_CTRL2.
EXTJSEL[2:0] bits
ADC_CTRL2.
EXTRSEL[2:0] bits
T
IM
1
_
CH
1
T
IM
1
_
CH
2
T
IM
1
_
CH
3
T
IM
2
_
CH
2
T
IM
4
_
CH
4
T
IM
3
_
T
R
G
O
E
X
T
I_
11
T
IM
1
_
CH
4
T
IM
4
_
CH
3
T
IM
8
_
CH
2
T
IM
8
_
CH
4
T
IM
5
_
T
R
G
O
T
IM
3
_
CH
1
T
IM
2
_
CH
3
T
IM
1
_
CH
3
T
IM
8
_
CH
1
T
IM
5
_
CH
1
T
IM
8
_
T
R
G
O
ADC_CTRL2.
EXTJSEL[2:0] bits
ADC_CTRL2.
EXTRSEL[2:0] bits
A
D
C
_
C
T
R
L
2
.
E
X
T
J
T
R
IG
b
it
A
D
C
_
C
T
R
L
2
.
E
X
T
R
T
R
IG
b
it
T
IM
1
_
T
R
G
O
Trigger signal for ADC1 and ADC2
Trigger signal for ADC3 and ADC4
V
BAT/2
T
IM
5_
CC
4
E
X
T
I_
14
AFIO_RMP_CFG4.
ADCx_ETRI bit
T
IM
5_
CH
3
AFIO_RMP_CFG4.
ADCx_ETRR bit
E
X
T
I_
10