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Nations Technologies Inc.
Tel
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+86-755-86309900
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
pin reset methods. The default clock cycle of the output pulse is 18M/HCLK (when the HCLK is 144M, the pulse
width is 125ms). The function can check whether all nodes in the network are synchronized. Connect the PPS outputs
of both the master and slave devices to an oscilloscope to test the difference between the local slave clock and the
master clock.
25.4.10
Typical ethernet configuration flow example
After a power-on reset or system reset, the recommended configuration and startup process for Ethernet module is as
follows:
1.
Configure RCC module, enable HCLK clock and Ethernet transmit/receive clock;
2.
Configure AFIO_RMP_CFG to select MII or RMII connection mode, and map corresponding function pins to
alternate functions;
3.
Poll ETH_DMABUSMOD register until ETH_DMABUSMOD.SWR bit is reset after reset is completed;
4.
Get and configure PHY register parameters:
According to the HCLK frequency, configure SMI clock frequency, communicate with the external PHY and
access the corresponding registers, confirm whether the external PHY supports half/full duplex working mode,
10Mbps/100Mbps communication speed, etc., and configure the information of the external PHY register to the
ETH_MACCFG register.
5.
Initialize Ethernet DMA module:
Configure ETH_DMABUSMOD, ETH_DMARXDLADDR, ETH_DMATXDLADDR, ETH_DMAOPMOD
registers to initialize DMA module for data transfer.
6.
Initialize physical memory space for storing descriptor list and data cache:
Based on the addresses in ETH_DMARXDLADDR and ETH_DMATXDLADDR registers, DMA is initialized
to hold transmit and receive descriptors (TDES0.OWN = 0 or RDES0.OWN = 1) and data buffers.
7.
Enable the MAC and DMA modules to start data transfer:
Start MAC transmitter and receiver by setting ETH_MACCFG.TE and ETH_MACCFG.RE to 1, and enable
DMA transmission and reception by setting ETH_DMAOPMOD.ST and ETH_DMAOPMOD.SR to 1.
8.
When transmit frame data:
a)
Select one or more transmit descriptors, write the transmit frame data to the buffer address specified in the
transmit descriptor, and set TDES0.OWN in transmit descriptor to make DMA occupy descriptor;
b)
Write any value into ETH_DMATXPD register to make TxDMA exit the suspend mode and start sending
data;
c)
It is possible to confirm whether the transmission of current frame is completed by polling TDES0.OWN
of current descriptor until it is reset or polling ETH_DMASTS.TI until it is set (only applicable when
TDES1.IC is 1).
9.
When receive frame data:
a)
View first receive descriptor in descriptor list (the address of descriptor can be obtained through the
