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/
838
Nations Technologies Inc.
Tel
:
+86-755-86309900
:
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
011: TIM2_CC2 event; 111: SWSTRRCH.
Trigger configuration for ADC3 and ADC4:
000: TIM3_CC1 event; 100: TIM8_TRGO event;
001: TIM2_CC3 event; 101: TIM5_CC1 event;
010: TIM1_CC3 event; 110: EXTI line 10/TIM5_CC3 event;
011: TIM8_CC1 event; 111: SWSTRRCH.
16
Reserved
Reserved, the reset value must be maintained
15
EXTJTRIG
External trigger conversion mode for injected channels
This bit is set and cleared by software to enable or disable external triggering events that can
start injection sequence conversion.
0: Start conversion without external events.
1: Use an external event to start the conversion.
14:12
EXTJSEL[2:0]
External event select for injected sequence
These bits select the External event used to trigger the injected sequence conversion.
Trigger configuration for ADC1 and ADC2:
000: TIM1_TRGO event; 100: TIM3_CC4 event;
001: TIM1_CC4 event; 101: TIM4_TRGO event;
010: TIM2_TRGO event; 110: EXTI line 15/TIM8_CC4 event;
011: TIM2_CC1 event; 111: SWSTRRCH.
Trigger configuration for ADC3 and ADC4:
000: TIM3_TRGO event; 100: TIM8_CC4 event;
001: TIM1_CC4 event; 101: TIM5_TRGO event;
010: TIM4_CC3 event; 110: EXTI line 14/TIM5_CC4 event;
011: TIM8_CC2 event; 111: SWSTRRCH.
11
ALIG
Data alignment
This bit is set and cleared by the software. Refer to Table 9-3 and Table 9-4.
0: Right-aligned.
1: Left-aligned.
10:9
Reserved
Reserved, the reset value must be maintained
8
ENDMA
Direct memory access mode
This bit is set and cleared by the software. See the DMA Controller chapter for details.
0: Do not use DMA mode.
1: Use DMA mode.
7:3
Reserved
Reserved, the reset value must be maintained
2
ENCAL
A/D calibration
This bit is set by software to start calibration and cleared by hardware at the end of calibration.
0: Calibration completed;
1: Starts calibration.
1
CTU
Continuous conversion
This bit is set and cleared by the software. If this bit is set, the conversion continues until the bit
is cleared.
0: Single conversion mode.