Nations N32G45 Series, User Manual

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552 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
CAN master status register (CAN_MSTS)
Address offset: 0x04
Reset value: 0x0000c02
Bit Field Name Description
31:12 Reserved Reserved, the reset value must be maintained.
11 RXS CAN Rx signal
This bit reflects the actual level of the CAN receive pin (CAN_RX).
10 LSMP Last sample point
The last sampled value of the CAN receive pin (corresponding to the value of the
current receive bit).
9 RXMD Receive mode
if this bit equals to 1 indicates CAN is currently the receiver.
8 TXMD Transmit mode
if this bit equals to 1 indicates CAN is currently the transmitter.
7:5 Reserved Reserved, the reset value must be maintained.
4 SLAKINT Sleep acknowledge interrupt
When CAN_INTE.SLKITE=1, once CAN enters sleep mode, hardware will set
this bit, and then the corresponding interrupt will be triggered. When this bit is
set, if the CAN_INTE.SLKITE bit is set, a state change interrupt will be
generated.
Software can clear this bit, and hardware also clears this bit when
CAN_MSTS.SLPAK bit is cleared.
Notes : When CAN_INTE.SLKITE=0, this bit should not be queried, but the
CAN_MSTS.SLPAK bit should be queried to know the sleep state.
3 WKUINT Wakeup interrupt
When CAN is in sleep state, once the start of frame bit (SOF) is detected, the
hardware will set this bit; And if the CAN_INTE.WKUITE bit is set, a state
change interrupt is generated.
This bit is cleared by software.
2 ERRINT Error interrupt
When an error is detected, a bit of the CAN_ESTS register will be set, and if the
corresponding interrupt enable bit of the CAN_INTE register is also set, the
hardware will set this bit; If the CAN_INTE.ERRITE bit is set, a state change
interrupt is generated. This bit is cleared by software.
1 SLPAK Sleep acknowledge