Nations N32G45 Series, User Manual

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518 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit Field Name Description
suspend signal.
10 RST USB reset interrupt flag
This bit is set by hardware when a USB reset signal is detected.
Note:
1
、
Software can read and write this bit, but only writing 0 is valid, and writing 1 is
invalid.
2
、
When the USB reset interrupt is generated, the address and endpoint registers of
the device will be reset, but the configuration registers will not be reset unless
cleared by software.
9 SOF Start of frame interrupt flag
This bit is set by hardware when a PID SOF token packet is detected on the USB bus.
Note:
1
、
Software can read and write this bit, but only writing 0 is valid, and writing 1 is
invalid.
8 ESOF Expected start of frame interrupt flag
This bit is set by hardware when the USB module does not receive the expected PID
SOF token packet.
Note:
1
、
Software can read and write this bit, but only writing 0 is valid, and writing 1 is
invalid.
2
、
When the USB module does not receive the PID SOF token packet for 3ms in a
row, that is, 3 ESOF interrupts occur in a row, and a SUSPD interrupt will be
generated.
7
：
5 Reserved Reserved, the reset value must be maintained.
4 DIR Transmission direction
0: IN packet transfer is completed, and USB_EPn.CTRS_TX is set by hardware
1: OUT packet transfer is complete, and USB_EPn.CTRS_RX is set by hardware
Note:
1
、
Software can only read this bit, not write this bit.
2
、
When USB_EPn.CTRS_TX and USB_EPn.CTRS_RX are set at the same time, it
indicates that there are OUT group and IN group at the same time.
3
：
0 EP_ID[3:0] Endpoint number
After the USB module completes the data transmission and generates an interrupt, it
is written by the hardware according to the endpoint number of the interrupt request.
Note:
1
、
Software can only read this bit, not write this bit.
2
、
When multiple endpoint requests are interrupted at the same time, the hardware
writes the endpoint number with the highest priority. Isochronous endpoints and
double-buffered bulk endpoints have high priority, other endpoints have low
priority (the lower the endpoint number, the higher the priority).