780
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
27
MMCI
MMC status.
This bit indicates that an interrupt event has occurred in the MMC module of the
MAC controller. Software must read the corresponding register of the MAC
controller, find the source of the interrupt and clear it, in order to clear this bit. When
this bit is set, an interrupt is generated if the corresponding interrupt is enabled.
0: No MMC interrupt event occurred.
1: An MMC interrupt event has occurred.
26
Reserved
Reserved, the reset value must be maintained.
25:23
EB[2:0]
Error bit status.
When ETH_DMASTS.FBI = 1, these bits will do error type resolution for bus
response errors on the AHB bus, these bits will not trigger an interrupt.
EB[0]:
0: Error during RxDMA transfer of data.
1: Error during TxDMA transfer of data.
EB[1]:
0: Error during write transfer.
1: Error during read transfer.
EB[2]:
0: Error during data buffer access.
1: Error during descriptor access.
22:20
TPS[2:0]
Transmit process status.
These bits indicate the status of TxDMA.
000: Stop, receive reset or stop transmitting command.
001: Running, getting transmit descriptor.
010: Running, waiting status information.
011: Running, data in memory is being read and stored in TxFIFO.
100, 101: Reserved.
110: Pause, transmit descriptor unavailable or transmit buffer data underflow.
111: Running, closing transmit descriptor.
19:17
RPS[2:0]
Receive process status.
These bits indicate the status of RxDMA.
000: Stop, receive reset or stop receiving command.
001: Running, getting receive descriptor.
010: Reserved.
011: Running, waiting receive packets.
100: Pause, receive descriptor not available.
101: Running, closing receive descriptor.
110: Reserved.
111: Running, forwarding received packets from RxFIFO to memory.
16
NIS
Normal interrupt summary.
With the corresponding interrupt enabled in the ETH_DMAINTEN register, the
normal interrupt summary bits are the logical OR of the following bit values:
