Nations N32G45 Series, User Manual

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Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
3. Wait for SPI_STS.TE bit to be set to '1', and write the second data to be sent into SPI_DAT. Repeat this operation
to send subsequent data;
4. After writing the last data to SPI_DAT, wait for SPI_STS.TE bit to set '1'; then wait for SPI_STS.BUSY bit to
be cleared to complete the transmission of all data.
The process of data sending can also be implemented in the interrupt handler generated by the rising edge of the TE
flag.
Figure 21-6 Schematic diagram of TE/BUSY change when the host transmits continuously in one-way only mode

Master two-wire one-way receive-only mode (SPI_CTRL1.MSEL = 1, SPI_CTRL1.BIDIRMODE = 0,
SPI_CTRL1.RONLY = 1)
When SPI_CTRL1.SPIEN = 1, the receiving process starts. The data bits from the MISO pin are sequentially shifted
into the shift register and then loaded into the SPI_DAT register(receive buffer) in parallel. The software operation
process is as follows:
Enable the receive-only mode (SPI_CTRL1.RONLY = 1).
Enable SPI module, set SPI_CTRL1.SPIEN = 1: in master mode, SCLK clock signal is generated immediately, and
serial data is continuously received before SPI is turned off (SPI_CTRL1.SPIEN = 0); in slave mode, serial data is
continuously received when the SPI master device pulls low the NSS signal and generates SCLK clock.
Wait for SPI_STS.RNE bit to be set to '1', read the SPI_DAT register to get the received data, and the SPI_STS.RNE
bit will be cleared by hardware while reading SPI_DAT register. Repeat this operation to receive all data.
The process of data receiving can also be implemented in the interrupt handler generated by the rising edge of the
RNE flag (SPI_STS.RNE).
Figure 21-7 Schematic diagram of RNE change when continuous transmission occurs in receive-only mode (BIDIRMODE = 0 and
b0 b2 b1 b3 b4 b6 b5 b0 b7 b1 b2 b3 b5 b4 b6 b7 b1 b0 b3 b2 b4 b5 b7 b6
DATA1=0x11 DATA2=0x22 DATA3=0x33
SCK
MISO/MOSI
(out)
TE flag
Tx buffer
（
write SPI_DAT
）
BUSY flag
Master mode
：
CLKPOL=1.CLKPHA=1
The flag set/clear by hardware
Set by hardware Clear by software
Write 0x11 into SPI_DAT
Wait until TE=1,Write 0x22 into SPI_DAT
Wait until TE=1,Write 0x33 into SPI_DAT
Wait TX=1
Wait BUSY=0
0x22 0x33 0x11