445
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 18-7 SDIO adapter
The HCLK/2 of the AHB bus is used as the clock of the adapter register and FIFO, and the SDIOCLK(equal to
HCLK) is used as the clock of the control unit, command channel and data channel.
The SDIO adapter includes five parts: control unit, adapter register module, command unit, data unit and data FIFO.
The signals output to the card bus are as follows:
SDIO_DAT[7:0]: The data signal line uses push-pull mode. By default, only SDIO_DAT0 is used for data
transfer after power-on or reset. The SDIO adapter can configure a wider data bus for data transfer after
initializing the host, using DAT0-DAT3 or DAT0-DAT7 (only for MMC V4.2). Note that the protocol of MMC
version V3.31 and previous versions only supports 1-bit data line (only SDIO_DAT0 can be used). When an SD
or SD I/O card is connected to the bus, SDIO_DAT0 or SDIO_DAT[3:0] can be used by the host to configure
data transfers.
SDIO_CMD, two operating modes:
Open-drain mode for initialization (only for MMC version V3.31 or earlier)
Push-pull mode for command transfer (SD/SD I/O cards and MMC V4.2 also use push-pull drive during
initialization)
SDIO_CLK: The clock provided to the card by the SDIO controller. One bit of command or data is sent directly
on the command line (SDIO_CMD) and all data lines per clock cycle. The variation range of the clock frequency
of different cards is different, as follows:
MMC V3.31 protocol, optional clock frequency between 0MHz and 20MHz;
MMC V4.0/4.2 protocol, optional clock frequency between 0MHz and 48MHz;
SD or SD I/O card, optional clock frequency between 0MHz and 25MHz.
The following table is the MMC/SD/SD I/O card bus pin definition:
SDIO adapter
Adapter
register
SDIOCLK
HCLK/2
SDIO_CLK
SDIO_CMD
SDIO_DAT[7:0]
FIFO
To AHB
interface
Ca
rd
B
us
Data channel
Command
channel
Control unit
