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Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
and transmit information to each other through these two wires. SDA and SCL are two-way wires, it should connected
to a current source or the positive of the power supply with a pull-up resistor. When the bus is idle, both lines are
high level. The output of device which is connected to the bus must have open drain or open collector to provide
wired-AND functionality. The data on I2C bus can reach 100 kbit/s in standard mode and 400kbit/s in fast mode.
Since devices of different processors may be connected to the I2C bus, the levels of logic '0' and logic '1' are not fixed
and depend on the actual level of VDD.
If the clock extending is allowed, the SCL line is pulled down which can be avoided the overload error during
receiving and the under load error during transmission.
For example, when in the transmission mode, if the transmit data register is empty and the byte transmit end bit is set
(I2C_STS1.TXDATE = 1, I2C_STS1.BSF = 1), the I2C interface keeps the clock line low before transmission to
wait for the software to read STS1 and write the data into the data register (both buffer and shift register are empty);
when In the receive mode, if the data register is not empty and the byte sending end bit is set (I2C_STS1.RXDATNE
= 1, I2C_STS1.BSF = 1), the I2C interface keeps the clock line low after receiving the data byte, waiting for the
software to read STS1, and then read the data register(buffer and shift register are full).
If clock extending is disable in slave mode, if the receive data register is not empty (I2C_STS1.RXDATNE = 1) in
the receive mode, and the data has not been read before receiving the next byte, an overrun error will issue and the
last word byte will be discarded. In transmit mode, if the transmit data register is empty (I2C_STS1.TXDATE = 1),
no new data is written into the data register before the next byte must be sent, an underrun error will issue. The same
byte will be send repeatedly. In this case, duplicate write conflicts are not controlled.
22.3.2
Software
communication
process
The data transmission of I2C device is divided into master and slave. Master is the device responsible for initializing
the transmission of data on the bus and generating clock signal. At this time, any addressed device is a slave. Whether
the I2C device is a master or a slave, it can send or receive data. Therefore, the I2C interface supports four operation
modes:
Slave transmitter mode
Slave receiver mode
Master transmitter mode
Master receiver mode
After system reset, I2C works in slave mode by default. The I2C interface is configured by software to send a start
bit on the bus, and then the interface automatically switches from the slave mode to the master mode. When arbitration
is lost or a stop signal is generated, the interface will switched to the slave mode from the receive mode.
The block diagram of I
2
C interface is shown in the figure below.
