778
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
Write any value to these bits to enable RxDMA receive query, which will query
whether the current descriptor (descriptor address is in the ETH_DMACHRXDESC
register) is occupied by the CPU. If not (RDES0.OWN = 1), the descriptor is available
and RxDMA exits the suspend state and resumes work. On the contrary
(RDES0.OWN = 0), the RxDMA returns to the suspended state and
ETH_DMASTS.RU is set to 1.
25.5.45
ETH DMA receive descriptor list address register
(ETH_DMARXDLADDR)
Address offset: 0x100C
Reset value: 0x0000 0000
The receive descriptor list register points to the beginning of the receive descriptor queue. Descriptor queues are
located in physical memory, and their addresses must be word-aligned. Writing to this register is only allowed when
reception is stopped. This register must be configured correctly before starting the RxDMA receive process.
Bit field
Name
Description
31:0
SRL[31:0]
Receive queue base address.
These bits contain the address of the first descriptor in the receive descriptor queue.
RxDMA ignores the lowest 2 bits and defaults to 0.
25.5.46
ETH DMA transmit descriptor list address register
(ETH_DMATXDLADDR)
Address offset: 0x1010
Reset value: 0x0000 0000
This register points to the start of the transmit descriptor queue. Descriptor queues are located in physical memory,
and their addresses must be word-aligned. Writing to this register is only allowed when transmission is stopped.
Before starting the TxDMA transmission process, this register must be configured correctly.
