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Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
on the data line during the transmission of the stop bit. If a parity error occurs, the smartcard will pull down the
data line when the transmitter samples the NACK signal, that is, within the time corresponding to the stop bit
on the bus, indicating that a framing error has occurred. The USART_STS.FEF is set together with the
USART_STS.RXDNE at the end of the 1.5th stop bit. The 1.5 stop bits were sampled at points 16, 17 and 18.
The 1.5 stop bits can be divided into two parts: one is 0.5 clock cycles, during which nothing is done. This is
followed by the stop bit of 1 clock cycle, which is sampled at the midpoint of this period of time. For details,
see 23.4.14 Smartcard mode.
4.
2 stop bits: the sampling of the 2 stop bits is completed at the 8th, 9th and 10th sampling points of the first stop
position. If a frame error is detected during the first stop bit, the frame error flag is set. The second stop bit does
not detect framing error. The USART_STS.RXNE flag will be set at the end of the first stop bit.
Receiver process
1.
Enable USART_CTRL1.UEN to activate USART;
2.
Configure the receiver's baud rate, data bit length, parity bit (optional), stop bit number or DMA configuration;
3.
Activate the receiver (USART_CTRL1.RXEN) and start looking for the start bit;
4.
The receiver receives 8-bit or 9-bit data according to the configuration of the data bit length, and the least
significant bit of the data is first shifted from the RX pin into the receive shift register;
5.
When the data of the received shift register is moved to the RDR register, USART_STS.RXDNE is set, and the
data can be read out. If USART_CTRL1.RXNEIEN is 1, an interrupt will be generated;
6.
When an overflow error, noise error, or frame error is detected in the received frame, the corresponding error
flag status bit will be set. If USART_CTRL1.RXEN is reset during data transmission, the data being received
will be lost;
7.
USART_STS.RXDNE is set after receiving data, and a read operation of USART_DAT can clear this bit:
During multi-buffer communication, the data register is cleared by the DMA read operation;
During single-buffer communication, it is cleared by software reading the USART_DAT register.
Idle frame detection
The receiver of the USART can detect idle frames. An interrupt is generated if USART_CTRL1.IDLEIEN is '1'.
USART_STS.IDLEF bit is cleared by a software sequence (read USART_STS register first, then read USART_DAT
register).
Break frame detection
The frame error flag(USART_STS.FEF) is set by hardware when the receiver detects a break frame. It can be cleared
by a software sequence (read USART_STS register first, then read USART_DAT register).
Framing error
A framing error occurs when a stop bit is not received and recognized at the expected time. At this time, the frame
error flag USART_STS.FEF will be set by hardware, and the invalid data will be transferred from the shift register
to the USART_DAT register. During single-byte communication, no framing error interrupt will be generated because
it occurs with USART_STS.RXDNE and the hardware will generate an interrupt when the USART_STS.RXDNE
flag is set. In multi-buffer communication mode, an interrupt will be generated if the USART_CTRL3.ERRIEN bit
