453
/
838
Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Wait_S:
In this state, the DPSM waits for the data FIFO empty flag to be invalid or the end of the data transfer. If the
data counter is 0, the DPSM enters the idle state; otherwise, the DPSM waits for the data FIFO empty flag to
disappear before entering the sending state.
Note: DPSM will remain in Wait_S state for at least 2 clock cycles to meet the timing requirements of NWR.
NWR is the interval from receiving the response from the card to when the host starts data transmission.
Send:
In this state, the DPSM starts sending data to the card device. Depending on the setting of the transfer mode bits
in the data control register, the data transfer mode can be block transfer or stream transfer:
In block mode, when the data block counter reaches 0, the DPSM sends the internally generated CRC code,
followed by the end bit, and enters the busy state.
In streaming mode, when the enable bit is high and the data counter is not 0, the DPSM sends data to the
card device, and then enters the idle state.
If a FIFO underflow error occurs, the DPSM sets the FIFO error flag and enters the idle state.
Busy:
In this state, the DPSM waits for the CRC status flag:
If the correct CRC status is not received, the DPSM enters the idle state and sets the CRC failure status
flag.
If the correct CRC status is received, and the card is not busy (SDIO_DAT0 is not low), the DPSM enters
the Wait_S state.
If the correct CRC status is not received, the DPSM enters the idle state and sets the CRC failure status
flag.
If the data timeout DPSM sets the data timeout flag and enters the idle state.
When the DPSM is in Wait_R or busy state, the data timer is enabled and can generate a data timeout error:
When sending data, if the DPSM is in a busy state and exceeds the timeout interval set by the program, a
timeout will occur.
When receiving data, if all data is not received and DPSM is in Wait_R state for more than the timeout
interval set by the program, a timeout will occur
Data
Data can be transferred from the host to the card and vice versa.
Data is transmitted over the data line. Data is stored in a 32-word depth FIFO, each word is 32 bits wide.
Table 18-3 Data Token Format
Description
Start bit
Data
CRC16
End bit
Block Data
0
-
Yes
1
Stream Data
0
-
No
1
