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Nations Technologies Inc.
Tel
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+86-755-86309900
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
LSI calibration
The internal low-speed oscillator LSI can be calibrated to compensate for its frequency offset to obtain an RTC time
base with acceptable accuracy, and an independent watchdog (IWDG) timeout (when these peripherals are clocked
from the LSI).
Calibration can be achieved by measuring the LSI clock frequency using the TIM5's input clock (TIM5_CLK). The
measurement is guaranteed by the accuracy of the HSE. The software can obtain the accurate RTC clock base by
adjusting the 20 bit prescaler of the RTC, and obtain the accurate independent watchdog (IWDG) timeout time by
calculation.
The LSI calibration steps are as follows:
1. Turn on TIM5 and set channel 4 to input capture mode;
2. Set the AFIO_RMP_CFG.TIM5CH4_RMP bit to 1, and connect the LSI to channel 4 of TIM5 internally;
3. Measure LSI clock frequency through TIM5 capture/compare 4 events or interrupts;
4. Set the 20 bit prescaler based on the measurement results and the desired RTC time base and independent watchdog
timeout.
6.2.7
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as the system clock. It cannot be stopped when the clock source is
used directly or indirectly through the PLL as the system clock.
Switching from one clock source to another will only occur when the target clock source is ready (either after a delay
to start the stabilization phase or PLL stabilization). When the selected clock source is not ready, the switching of the
system clock will not occur until the target clock source is ready.
Status bits in the clock control register (RCC_CTRL) indicate which clock is ready and which clock is currently used
as the system clock.
6.2.8
Clock security system (CLKSS)
Clock security system can be activated by software by setting the RCC_CTRL.CLKSSEN bit. Once activated, the
clock detector is enabled after the startup delay of the HSE oscillator, and disabled when the HSE clock is turned off.
If the HSE clock fails, the HSE oscillator will be automatically turned off, and a clock failure event will be sent to
the break input of the advanced timers (TIM1 and TIM8), and the Clock Security System Interrupt CLKSSIF will be
generated, allowing the software to execute rescue operations. The CLKSSIF interrupt is connected to the NMI (Non-
Maskable Interrupt) interrupt of the Cortex™-M4.
Once the CSS is activated and the HSE clock fails, the CSS interrupt is generated and the NMI is automatically
generated. The NMI will be executed continuously until the CSS interrupt pending bit is cleared. Therefore, it is
necessary to clear the CSS interrupt by setting the RCC_CLKINT.CLKSSICLR bit in the NMI handler.
If the HSE oscillator is directly or indirectly used as the system clock (indirectly means: it is used as the PLL input
clock, and the PLL clock is used as the system clock), the clock failure will cause a switch of the system clock to the
HSI oscillator and the disabling of the external HSE oscillator. If HSE clock (divided or not) is selected as PLL input
