Nations N32G45 Series, User Manual

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101 / 838
Nations Technologies Inc.
Tel
：
+86-755-86309900
Email
：
info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
The source of the reset event can be identified by looking at the reset status flag bits in the RCC_CTRLSTS control
status register.
Software reset
A software reset can be generated by setting the SYSRESETREQ bit in Cortex™-M4 Application Interrupt and Reset
Control Register. Refer to Cortex™-M4 technical reference manual for further information.
Low-power management reset
Low-power management reset can be generated by using the following methods:

Generate low power management reset when entering STANDBY mode: This reset is enabled by setting the
nRST_STDBY bit in the user option byte. At this time, even if the procedure to enter STANDBY mode is
performed, the system will be reset instead of entering STANDBY mode.

Generate low power management reset when entering STOP0/STOP2 mode: This reset is enabled by setting the
nRST_STOP bit in the user option byte. At this time, even if the process to enter STOP0/STOP2 mode is
performed, the system will be reset instead of entering STOP0/STOP2 mode.
The system reset signal provided to the chip is output on the NRST pin. The pulse generator guarantees a minimum
reset pulse duration of 20μs for each reset source (external or internal). For external reset, the reset pulse is generated
while the NRST pin is asserted low.
The Figure below shows the system reset generation circuit.
Figure 6-1 System reset generation
6.1.3 Backup domain reset
The backup domain has two dedicated resets that only affect the backup domain (see Figure 4-1 Power Supply Block
Diagram).
Pulse
Generator
(min 20us)
RAM parity error
reset
IWDG reset
WWDG reset
SW reset
Low Power
Management reset
MMU reset
Backup domain EMC
reset
NRST PIN
Schmit Filter
System Reset
VDD/VDDA
Power reset
Retention domain
EMC reset
BOR reset