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Nations Technologies Inc.
Tel
：
+86-755-86309900
：
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Figure 9-2 ADC clock
9.3.2
ADC switch control
You can proceed to the next step only after the power-up process is complete. You can check if the power-up is
complete by polling the ADC_CTRL3.RDY bit.
You can set the ADC_CTRL2.ON bit to turn on the ADC. When the ADC_CTRL2.ON bit is set for the first time, it
wakes up the ADC from the power-off state. After a power-on delay of ADC (t
STAB
), and the conversion begins when
the ADC_CTRL2.ON bit is set again.
The conversion can be stopped by clearing the ADC_CTRL2.ONbit and placing the ADC in power-off mode. In this
mode, the ADC consumes almost no power (just a few μA). Power-down can be checked by polling the
ADC_CTRL3.PDRDY bit.
When the ADC is disabled, the default mode is power-down. In this mode, as long as the power is on, there is no
need to re-calibrate, and the calibration value is automatically maintained in the ADC. To further reduce power
consumption, the ADC has a deep sleep mode. When ADC Disable is in deep sleep mode, the calibration value inside
the ADC is lost and needs to be recalibrated. Deep sleep saves about 0.2μA of power consumption.
Note: That when in dual ADC mode, it is best to select the same sleep mode for both ADCs. Register
ADC_CTRL3.DPWMOD which controls ADC deep sleep mode.
9.3.3
Channel selection
Each channel can be configured as a regular sequence and an injection sequence.
Injection sequence
consists of multiple conversions, up to a maximum of 4.
The ADC_JSEQ register specifies the
injection channel and the conversion order of the injection channel. The ADC_JSEQ.JLEN[1:0] bits specified
injection sequence length.
DIV
1MCLK
ADC_1MCLK
HCLK
HCLK
PLL_DIV_CLK
ADC_CLK
