IDT Tsi578, User Manual

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3. Serial RapidIO Electrical Interface > Port Power Down 73
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
3.5.1.1 Global Registers to Program after Port Power Down
The following global registers must be re-programmed with the appropriate configuration values when
a port is reset:
• “RapidIO Component Tag CSR”
• “RapidIO Route LUT Attributes (Default Port) CSR”
• “RapidIO Switch Port Link Timeout Control CSR”
• “RapidIO Switch Port General Control CSR”
• “RapidIO Logical and Transport Layer Error Enable CSR”
• “RapidIO Port-Write Target Device ID CSR”
• “RapidIO Multicast Write ID x Register”
3.5.2 Special Conditions for Port 0 Power Down
Port 0 can only be powered down through register accesses and not through the SPn_PWRDN pin. Port
0 has the has following special conditions after it is powered down:
• The list of registers in “Default Configurations on Power Down” on page 72 can not be read while
port 0 is in reset
• After reset the listed registers must be re-written (like any other port that has been powered down)
3.5.3 Power-Down Options
The following power-down options are available on a port:
• A port’s main logic can be powered down at boot up through the SP{n}_PWRDN pins.
• The default configuration provided by the pins can be changed using the PWDN_X4 and
PWDN_X1 bits in the
“SRIO MAC x Digital Loopback and Clock Selection Register” . This can
occur during a boot load using an EEPROM on the I
2
C bus, or during normal operation through a
register write.
3.5.4 Configuration and Operation Through Power-down
The transceivers for the individual bit lanes can be powered down when they are not used. All valid
power-down scenarios are shown in
Table 6 .
Table 6: Serial Port Power-down Procedure
Mode for
Serial
Port n
Mode for
Serial
Port n+1 Required Power Down Configuration
4x N/A • De-assert the SP n _PWRDN pin and/or set the PWDN_X4 bit to 0 in the “SRIO MAC x Digital
Loopback and Clock Selection Register” on page 377 .
• To save power, assert the SP n+1 _PWRDN pin and/or set the PWDN_X1 bit to 1 in the “SRIO
MAC x Digital Loopback and Clock Selection Register” on page 377 . If this bit is not set,
Port n+1 consumes unnecessary power.