7. I
2
C Interface > Boot Load Sequence
169
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
7.8.4
EEPROM Device Detection
Once the bus is available, the Tsi578 tries to connect to the EEPROM. A START condition is generated
followed by BOOT_ADDR from the
. The upper 5 bits of that field reset to
0b10100 and the lower 2 bits are sampled from the I2C_SA[1:0] pins on exit from hard reset. This
allows up to four unique Tsi578 devices to boot from different EEPROMs on the same I
2
C bus. If an
ACK is received, which indicates the device is present, the sequence proceeds to the next phase. If
there is a bus collision, the loader returns to the Wait for Bus Idle phase because another master has the
bus. If a NACK is received, the process is retried from the Wait for Bus Idle phase up to 6 times in case
the device was busy. If six NACKs are received, the boot load is aborted and the BL_FAIL interrupt
status is asserted. An interrupt can also be sent to the Interrupt Controller if enabled using BL_FAIL in
the
.
7.8.5
Loading Register Data from EEPROM
Once the EEPROM is successfully addressed, the Tsi578 does not release the bus until the boot load is
complete. First, the peripheral address is set. The address resets to 0, so the first EEPROM accessed
must be loaded from address 0. The peripheral address is either 1 or 2 bytes depending on the state of
the I2C_MA pin, which much be set appropriately depending on the type of EEPROM connected.
The boot loader then switches to read mode and reads the first 8 bytes, expecting to find a count of the
number of registers to be initialized in the first 2 bytes, followed by 6 bytes of 0xFF. A validity check is
completed on this field — if the number of registers exceeds the maximum (see
), or if any of the last 6 bytes are not 0xFF, it is assumed the EEPROM does not contain boot
load data, the boot load is aborted and the BL_FAIL interrupt status is updated in the
. On these boot load status bits, the optional interrupt can be forwarded to the Interrupt
Controller if enabled in the
. If the register count was 0, the boot load is
ended successfully and the BL_OK interrupt status is updated. An optional interrupt can also be
forwarded to the Interrupt Controller if enabled in the
. For information
on the expected EEPROM data format used for boot loading, see
.
The boot loader continues by reading eight bytes of data for each register to be loaded, and increments
the peripheral address by 8. Depending on the PAGE_MODE field in the
the peripheral address is periodically reset by issuing a Restart, re-selecting the boot device, and
sending the updated peripheral address. On reset, the PAGE_MODE resets to a boundary of 8 such that
initially the peripheral address is updated to the device after every register is loaded (see
). In addition, for 1-byte peripheral addresses, if the BINC bit is 1, then when the peripheral
address crosses a 256-byte boundary (that is, when the 1-byte address rolls over to 0x00), the LSB 3
bits of the BOOT_ADDR are incremented and the device is re-addressed. This supports those
EEPROMs that use the lower 3 bits of their address as a 256-byte page indicator.
For each block of 8 bytes loaded, the first 4 bytes are the register address on the internal Tsi578 register
bus, and the next 4 bytes are the 32-bit data value to be written to the register. No checking is
completed for register address or data validity. As soon as all 8 bytes are read, the data is written to the
internal address, the peripheral address count is updated, and the register count is decremented. Once
the register count reaches 0 the boot load from the current EEPROM is complete, and, unless chaining
is invoked, the boot load sequence is complete, a STOP condition is issued to release the bus, and the
BL_OK interrupt status is updated. An optional interrupt can also be forwarded to the Interrupt
Controller if enabled in the
