B. Clocking > P_CLK Programming
494
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Effects of changing the P_CLK frequency and TVAL setting can be seen in
.
B.2.1.2
RapidIO Part 6: 1x/4x LP-Serial Physical Layer Specification Revision 1.3: Section
4.7.3.2 State Machine Variables and Functions
SILENCE_TIMER_DONE
The
RapidIO Interconnect Specification (Revision 1.3)
defines the SILENCE_TIMER_DONE as
follows:
Asserted when the SILENCE_TIMER_EN has been continuously asserted for 120 +/- 40 µs and
the state machine is in the SILENT state. The assertion of SILENCE_TIMER_DONE causes
SILENCE_TIMER_EN to be de-asserted. When the state machine is not in the SILENT state,
SILENCE_TIMER_DONE is de-asserted
IDT Implementation
The Tsi578’s silence timer does not have user programmable registers. The silence timer is sourced
from the P_CLK and any changes to P_CLK are directly reflected in the timer timeout period.
Table 54: Timer Values with P_CLK and TVAL Variations
P_CLK Setting
TVAL Setting
Equation
Timer Value
25 MHz
2,343,750 (0x23C346)
32/25 x 2,343,750
3 seconds
25 MHz
4,687,500 (0x47868C)
32/25 x 4,687,500
6 seconds
50 MHz
4,687,500 (0x47868C)
32/50 x 4,687,500
3 seconds
50 MHz
9,375,000 (0x8F0D18)
32/50 x 9,375,000
6 seconds
50 MHz
16,777,215 (0xFFFFFF)
32/50 x 16,777,215
10.4 seconds
100 MHz
9,375,000 (0x8F0D18)
32/100 x 9,375,000
3 seconds
100 MHz
16,777,215 (0xFFFFFF)
32/100 x 16,777,215
5.4 seconds
