12. Serial RapidIO Registers > IDT-Specific Performance Registers
355
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.9.13
RapidIO Port x Receiver Input Queue Depth Threshold Register
Queue depth registers are designed to allow for the rapid detection and notification of congestion.
This register sets the Receiver Queue Depth threshold, which is used in conjunction with
Port x Receiver Input Queue Congestion Status Register”
to monitor congestion on the input buffers.
This register also sets the CONG_PERIOD, which is used in conjunction with the
Receiver Input Queue Congestion Period Register”
to determine how long the input buffers have been
in a congestion state.
Register name: SP{0..15}_RX_Q_D_THRESH
Reset value: 0x0000_0000
Register offset: 13090, 13190, 13290, 13390, 13490,
13590, 13690, 13790, 13890, 13990, 13A90,
13B90, 13C90, 13D90, 13E90, 13F90
Bits
0
1
2
3
4
5
6
7
00:7
CONG_PERIOD
8:15
CONG_PERIOD
16:23
DEPTH
Reserved
24:31
Reserved
Bits
Name
Description
Type
Reset
Value
0:15
CONG_PERIOD
This value is programmed by SW to indicate the maximum
number of clock cycles that the output buffer can be in a
continuous congestion state. The congestion state is
determined based on the DEPTH and SPx_RX_Q_STATUS.
The programmed CONG_PERIOD value is then used as
follows:
0000 = CONG_PERIOD_CTR is disabled.
0001= For every clock cycle (for a 4x port operating at 3.125
Gbaud, this is 3.2 ns) that the output buffer is in continuous
congestion state, increment the CONG_PERIOD_CTR by 1.
FFFF = For every 64K clock cycles (for a 4x port operating at
3.125 Gbaud, this is 209.7 usec) that the output buffer is in
continuous congestion state, increment the
CONG_PERIOD_CTR by 1.
R/W
0x0000
