7. I
2
C Interface > Tsi578 as I
2
C Master
149
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
The overall procedure is to configure the device through the
C Master Configuration Register”
the data to be written in the
C Master Transmit Data Register”
(only needed for write operations),
then load the
with the specific transaction information and have the
START bit in that register set to 1. This initiates the master transaction. Software usually then waits for
a master-related interrupt to know when the transaction has completed, or the status can be polled using
the
. If the operation was a read, the data can then be retrieved by reading
C Master Receive Data Register”
Once a master operation is started, it cannot be aborted by software except when the I
2
C Interface is
reset using the
. Reset using the
is not recommended,
however, since it can leave the I
2
C bus in a state that makes it difficult to ensure that all devices are
back to an idle state.
7.4.1
Example EEPROM Read and Write
This section shows example pseudocode for writing and reading the EEPROM. This example is
configured in the context of register writes that must be made during a boot load of the EEPROM.
7.4.1.1
Write Example
//Write 8 bytes to the EEPROM
w 1d114 0x0042FFFF // load the write data register with the write contents
w 1d10c 0xc4000000 // load the destination address in EEPROM and go
w 1d114 0xFFFFFFFF // load the next 4 bytes into the write data register
w 1d10c 0xc4000004 // load the destination address and go
7.4.1.2
Read Example
//Read the locations programmed above
w 1d10c 0x84000008 // set the start bit and address
r 1d110 [receive data] // get the received data
w 1d10c 0x8400000c // same again - set start with the address
w 1d10c [receive data] // get the received data
7.4.2
Master Clock Generation
The I
2
C clock (I2C_SCLK) for master operation is generated by dividing down the reference clock
(P_CLK). The reset value for the I2C_SCLK generates a nominal 100-kHz operating speed. The bus
speed is affected by external devices stretching the clock.
For master operations, the clock frequency can be changed by modifying the timing parameter registers
(see
). Operation above 100 kHz is possible but the Tsi578 does not implement all the
standards requirements for fast mode.
The internal delay required by an EEPROM device to complete a write operation to its
memory array must be managed by software. The I
2
C Interface only tracks the status of the
operation by the bus signals.
